Dynamic Memory - Microcomputer Structures - Lecture Slides, Slides of Microcomputers

Download Dynamic Memory - Microcomputer Structures - Lecture Slides and more Slides Microcomputers in PDF only on Docsity!

Dynamic Memory

Dynamic Memory

• In chapter 7 of 2 nd^ Edition of text.
• VLSI of DRAM
• How implemented
• Timing concerns
• Sample system

The storage transistor

• Why it leaks
  • The storage transistor
• The input transistor
• Leakage is through reversed biased p-n junction

DRAM Memory system

• Low cost random access memory
• Usually large size memory
• Common sizes
  • 256K x 1-bit, 512K x 1-bit, 1M x 1-bit, 1M x 4-bits
• Requires facility to “refresh” the memory
• Address pins are typically multiplexed
  • Chips have a RAS* and CAS* input

DRAM System

• Note- chips often have separate data in and data out pins.

Timing

Read Cycle Timing

W* Timing in a read cycle

• Needed for refresh

Detailed write cycle timing

Generating signal timing

Refresh methods

• RAS* only refresh
• CAS* before RAS* refreshing
  • Avoids the need for a row-refresh address generator
• Special DRAM control logic called a DRAM controller

Memory Subsystem