Instruction Set Two - Microcomputer Structures - Lecture Slides, Slides of Microcomputers

Download Instruction Set Two - Microcomputer Structures - Lecture Slides and more Slides Microcomputers in PDF only on Docsity!

9/20/6 Lecture 3 - Instruction Set - Al 1

Instruction Set (2)

9/20/6 Lecture 3 - Instruction Set - Al 2

Lecture Overview

 The 68000 Instruction Set continued

 The understand and effectively use an

architecture must understand the register set

and the instruction set.

 Last time we looked at data movement and

arithmetic instructions

 Now cover remaining instructions

9/20/6 Lecture 3 - Instruction Set - Al 4

Integer Arithmetic Operations

 Conventional set of integer arithmetic ops

 Act on 8, 16, or 32 bit operands

 ADD - add source and destination and place

result in destination

 Both can be data registers  At least one must be a data register

9/20/6 Lecture 3 - Instruction Set - Al 5

Arithmetic

 ADDA – destination of add is an address

register

 ADDQ – add a literal value in the range 1 to 8

to the contents of a memory location or

register.

 ADDQ #4, D

 Speed is faster than ADD #4, D

9/20/6 Lecture 3 - Instruction Set - Al 7

ARITHMETIC

 CLR – Loads the target with 0

 DIVS, DIVU – Integer division, signed or

unsigned

 DIVU ,Dn -32-bit longword in Dn is divided by the low order 16 bits at . Quotient is 16-bits and depostied in low-order word of destination

9/20/6 Lecture 3 - Instruction Set - Al 8

ARITHMETIC

 MULS, MULU – multiply signed or unsigned

 SUB, SUBA, SUBQ, SUBI, SUBX – the subtractions equivalents of ADD

 NEG – Take the 2’s complement of target  NEGX – Two’s complement with X bit  EXT – sign extend low-order byte for word of destination

9/20/6 Lecture 3 - Instruction Set - Al 10

Logical Operations

 Boolean operation that treat data as binary

 Uses standard addressing modes for source

and destination

 With immediate addressing can be applied to

the contents of the SR or CCR

 An AND with xxx0xxx clears selected bits

 An OR with xxx1xxx sets selected bits

 An EOR toggles the selected bits

9/20/6 Lecture 3 - Instruction Set - Al 11

Shift Operations

 All bits of the operand are moved one or more

places as specified in the instruction

 Shifts are either logical, arithmetic or circular

 Figure 3-17 gives examples of shifts

 Forms

 ASL Dx,Dy shift Dy by Dx bits  ASL #, Dy shift Dy by #data bits  ASL shift by 1 place

9/20/6 Lecture 3 - Instruction Set - Al 13

Program Control

 Compare Instructions

 These instructions test data and set the CCR  CMP – compare source and destination operands  CMPA – compare address – second operands is an address register  CMPM – compare memory with memory  CMPI – compare register or memory, i.e. , with a specified value

9/20/6 Lecture 3 - Instruction Set - Al 14

Program Control (2)

 Branch Instructions

 Bcc Branch to label on condition true  14 versions where cc stands for one of 14 logical conditions  CC,CS,NE,EQ,PL,MI,HI,LS,GT,LT,GE,LE,VC,VS  Table 2.4 page 68  BRA Branch always  DBcc Dn, Test condition cc, decrement, and branch  WHAT MIGHT THIS BE USEFUL FOR?????  cc specifies which bit(s) of the cc are used

9/20/6 Lecture 3 - Instruction Set - Al 16

Subroutines

 JSR causes the address of the next

instruction (the return address) to be stacked

on the stack pointed to by A

 BSR is same except for addressing mode

allowed for

 BSR GetChar

 RTS return from subroutine

9/20/6 Lecture 3 - Instruction Set - Al 17

Example of start of subroutine

In calling program BSR GET_DATA

GET_DATA MOVE.W MOVE.L CCR,D1-D7/A0-(A7)-A6, - (A7)

MOVE.L RTR (A7)+, D1-D7/A0-A

Note that RTR restores the CCR.

9/20/6 Lecture 3 - Instruction Set - Al 19

RTS and RTR

 RTS – Return from subroutine

 Loads return address (on the top of the stack) in to program counter

 RTR – Return and restore condition codes

 Loads CCR from top of stack (1 word)  And then loads return address

Assignment HW

 For turn in

 Problem 2-52 Write a sequence of instructions to reverse the order of the bits of register D0. That is  D0(0)  D0(31)  D0(1)  D0(30)  D0(2)  D0(29)  …  D0(31)  D0(0) 9/20/6 Lecture 3 - Instruction Set - Al 20