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UNIT – V
BASIC PROCESSING UNIT: Some Fundamental Concepts, Execution of a Complete Instruction, Multiple-Bus Organization, Hardwired Control, Micro programmed Control, PIPELINING: Basic Concepts, Data Hazards, Instruction Hazards, Influence on Instructions Sets, Data path and Control Considerations, Superscalar Operations, Performance Considerations 2 MARKS
1. What do you mean by micro-operation? To perform fetch, decode and execute cycles the processor unit has to perform set of operations called micro-operation. 2. Define Processor. It executes machine instructions and coordinates the activities of other units. It is also called as instruction set processor or central processing unit (CPU). 3. What is Data path? The data registers, ALU and the interconnecting bus are referred to as data path. 4. What is meant by program counter? It is a processor register mainly used for execution. It stores the address of the next instruction to be executed. After fetching an instruction the content of the PC are updated to point to the next instruction in the sequence. 5. Define IR? IR is an instruction register. To execute an instruction the processor fetches the contents of the memory location pointed by the PC. The contents of this location are interpreted as an instruction to be executed. They are loaded into the IR. 6. What is micro program? (Apr 13) A sequence of one or more micro operations designed to control specific operation, such as addition, multiplication is called a micro program. 7. What do you mean by hardwired control unit? In the hardwired control, the control units use fixed logic circuits to interpret instructions and generate control signals from them. 8. Define microinstruction? It is to assign one bit position to each control signal required in the CPU. However, This scheme has one serious drawback – assigning individual bits to each control signal results in long micro instructions, because the number of required signal is usually large. Moreover, only few bits are used in any given instruction .The solution of this problem is to group the control signals. 9. List the two techniques used for grouping of control signals 1. Control signals: IN and OUT signals 2. Gating signals: Read, write, clear A, set carry in, continue operation etc. 10. Write down the steps to execute an instruction. 11. Define fetch step. To perform the execution of the instruction we have to fetch the content from the memory and store that content into the processor register IR. This is known as fetching phase. instruction registers. IR ╔ PC ╗ Increment the PC value by 4 to point out the next instruction in the program. P [PC]+
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12. What is meant by execution phase? Carry out the actions specified by the instruction in the instruction in the instruction register is known as execution instruction 13. Define MAR, MDR? MAR means memory address register and MDR means memory data registers. These two are the processor registers that can be used in memory read and write operations. 14. Define register transfer and list out the signals used to do it. As instruction execution involves a sequence of steps in which data are transferred from one register to another register. Two control signals are used to place the contents of the registers on the bus or to load the data on the bus into the registers. The signals are Ri in, Ri out. 15. Write down the control sequence for Move (R1), R2. The control sequence is: R1 out, MAR in Read MDRoutE, WMFC MDRout, R2 in, 16. Write down the steps to transfer the content of register R1 to register R4. Enable the output of register R1 by setting R1 out to 1. This places the contents of R1 on the processor bus. Enable the input of register R4 by setting R4 into 1. This loads data from processor bus into register R4. 17. Define multiphase clocking. In some processor data transfers may use both the rising and falling edges of the clock. Two or more clock signals are needed to guarantee proper transfer of data. This is known as multiphase clocking. 18. Define MFC signal. To accommodate the validity in response time, the processor waits until it receives an indication that the requested Read operation has been completed. A control signal MFC (Memory Function Complete) is used for this purpose. 19. Write down the steps to execute Add (R3), R1 instruction. Fetch the instruction Fetch the first operand Perform the addition Load the result into R1. 20. Define register file. In multi bus architecture all the general purpose registers are called combined into a single clock called as register file. 21. Define interrupt? CPU supervises the other system components via special control lines. Whenever the CPU receives the signals from the IO device (i.e.) interrupt signals, it suspends the current execution of the program and performs the interrupt request. After process the interrupt request, CPU transfers from supervisor mode to user mode. 22. Define instruction cycle. (Nov 12) The sequence of operations involved in processing an instruction is called as an instruction cycle. It is divided into two phases: 1.fetch cycle 2. Execution cycle. The instruction is obtained from main memory during the fetch cycle. The execution cycle includes decoding the instruction, fetching any required operands, and performing the operation specified by the instructions opcode.
35. List out the situations that not increment the micro Pc value. When a new instruction is loaded into the IR, the micro PC is loaded with the starting address of the micro routine for that instruction. When a branch instruction is encountered and the branch condition is satisfied the micro Pc is loaded with the micro Pc is loaded with the branch target address. When an End instruction is encountered micro Pc is loaded with the address of the first CW in the micro routine for the instruction fetch cycle. 36. What is the drawback present in micro instruction s representation and how can we eliminate it? Assigning individual bits to each control signal results in long micro instruction s because the number of required signals is usually large. Moreover only a few bits are set 1. So the available bit space is poorly used. We can overcome this draw back by grouping the relevant control signals. 37. Define vertical organization. Highly encoded scheme groups more number of instruction s into a single group. So minimum number of groups is enough to represent instruction set. This is known as vertical organization. 38. What is meant by horizontal organization? Minimally encoded scheme groups minimum number of instruction s into single group. So we need more group to represent the instruction set. This is known as vertical organization. 39. Define bit OR ing technique. By using this technique we can modify the branch address. It use an Or gate to change the least significant bit of the specified instruction’s address to1, if the addressing mode is used. 40. Why it is need of pre fetch instruction? One drawback of micro programmed control is the slower operation because of the time it takes to fetchinstruction s from the control store. Faster operation is achieved if the next instruction is pre fetched while three current one is being executed. 41. Define emulation. Programs written in the machine language of M2 can be run on computer M1 that is M1 emulate M2.Emulation allows us to replace absolute equipments. 42. What is meant by micro programmed control? In some processor the control signals are generated by a program similar to machine language programs.This is known as micro programmed control. 43. Comparison between Hardwired and Micro programmed control contro
44. Write the register transfer sequence for storing a word in memory. Writing word into a memory location, the derived address is loaded into MAR. Then the data can be written are loaded into MDR and a write command is issued. Hence executing the instruction MOV R2, (R1) requires the following sequence R1out, MAR in R2out MDR in, write MDR out E, WMFC. The processor remains in step3 until the memory operation is completed and as MFC response is received. 45. What is a micro program sequencer? If each machine instruction is implemented by a microinstruction using a bit for each control word, a micro-program counter is sufficient to control sequencing. Advantage:Writing micro program is fairly simple because standard software techniques can be used. Disadvantage:Two major disadvantages exist.Large number of microinstructions and large control store Execution time is larger.Consider a more complicated example of a complex machine instruction ADD src,Rdst which adds the source operand to the contents of the destination register and result will be stored in the destination register. Assume that source operand can be specified in the following addressing modes register 2) autoincrement 3)autodecrement 4)indexed as well as the indirect forms of these four modes 46. What are the sequences of operations involved in processing an instruction constitutes an instruction cycle? The sequence of operations involved in processing an instruction constitutes an instruction cycle, which can be subdivided into 3 major phases:
- Fetch cycle
- Decode cycle
- Execute cycle 47. What are advantage and disadvantage of hardwired control and Micro programmed control? Advantages of Micro programmed control It simplifies the design of control unit. Thus it is both, cheaper and less error prone implement. Control functions are implemented in software rather than hardware. Disadvantages A micro programmed control unit is somewhat slower than the hardwired control unit, because time is required to access the microinstructions from CM. 48. What is the address sequencing capabilities required in control memory? Each microinstruction should explicitly or implicitly specify the next micro instruction to be used; such address sequencing capabilities are required in the control memory 49. In what ways Width and Height of the control memory can be reduced? To reduce the number of pins, the dynamic memory chips use multiplexed address inputs. The address is divided into two parts. High-order address bits-select a row in the cell array Low-order address bits-selet a column in the cell array A typical processor issues all bits of an address at the same time 50. List the advantages of Multi-bus organization. Compared to single-bus architecture, the using of multiple-bus architecture have a great advantage in speed and of course, will affect performance also. Instead of using single-bus architecture, It is more convenient to use multiple-bus architecture. Using multiple-bus architecture will make each device to connect to own bus, which means that each device will have its own bus.
54. Define Pipelining. Pipelining increases instruction throughput by performing multiple operations at the same time (in parallel), but does not reduce instruction latency (the time to complete a single instruction from start to finish) as it still must go through all steps. 55. Explain the role of cache memory in Pipelining? Each pipeline stage is expected to complete in one clock cycle. The clock period should be long enough to let the slowest pipeline stage to complete. Faster stages can only wait for the slowest one to complete. Since main memory is very slow compared to the execution, if each instruction needs to be fetched from main memory, pipeline is almost useless. Fortunately, we have cache. 56. What is hazard? Any condition that causes the pipeline to stall is called a hazard. 57. What is data hazard? A data hazard is any condition in which either the source or destination operands of an instruction are not available at the time expected in the pipeline. 58. What is instruction hazard? The pipeline may be stalled because of a delay in the availability of an instruction which results in cache miss. These hazards are called control hazards or instruction hazards. 59. What is structural hazard? Structural hazard arises in a situation when two instructions require use of a given hardware resource at the same time. 60. What is branch penalty? The time lost as result of a branch instruction is often referred to as branch penalty. The branch penalty is one clock cycle. For a longer pipeline, the branch penalty may be higher. 61. What is meant by dispatch unit? Dispatch unit is a separate unit, which takes instructions from the front of the queue and sends them to the execution unit. The dispatch unit also performs the decoding function. 62. Define the terms branch delay slot and delayed branching. The location following the branch instruction is called a branch delay slot. There maybe more than one branch delay slot, depending on the time it takes to execute a branch instruction. A technique called delayed branching can minimize the penalty incurred as a result of conditional branch instructions. The instructions in delay slots are always fetched. If there are no useful instructions, these are filled with NOP instructions. That is branching takes place one instruction later than where the branch instruction appears in the instruction sequence in the memory, hence “delayed branch”. 63. What is speculative execution? Speculative execution means that instructions are executed before the processor is certain that they are in the correct execution sequence. It must be noted that no processor registers or memory locations are updated until it is confirmed that these instructions should indeed be executed. 64. Define static and dynamic branch prediction. A decision on which way to predict the result of the branch may be made in hardware by observing whether the target address of the branch is lower than or higher than the address of the branch instruction. The branch prediction decision is always the same every time a given instruction is executed is called
static branch prediction. The approach in which the branch prediction decision may change depending on execution history is called dynamic branch prediction.
65. What is a 2-state algorithm? The branch prediction algorithms are to reduce the probability of making a wrong decision, to avoid fetching instructions that eventually have to be discarded. The algorithm may be described by the two-state machine. The two states are: LT: Branch is likely to be taken LNT: Branch is likely not to be taken 66. Represent a 4-state machine algorithm. The four states are: ST: Strongly likely to be taken LT: Likely to be taken LNT: Likely not to be taken SNT Strongly likely not to be taken 67. What is misprediction? The state information used in dynamic branch prediction may be recorded in a look-up table. It is possible for two branch instructions to share the same table entry. This leads to branch being mispredicted, but it does not cause an error in execution. Misprediction only introduces a small delay in execution time. 68. State the advantage and disadvantage of complex addressing modes. Complex addressing modes involve several accesses to memory that do not necessarily lead to faster execution. The main advantage is that they reduce the number of instructions needed to perform a given task and thereby reduce the program space needed in the main memory. The disadvantage is that
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1. Explain about Single bus organization of the Data path inside a processor: To execute an instruction, the processor has to perform the following steps: Fetch the contents of the memory location pointed to by the pc. The contents of this location are interpreted as an instruction to be executed. Hence, they are loaded in to the IR. Symbolically, this can be written as IR <- [[PC]] o Assuming that the memory is byte addressable increment the contents of the pc by 4 that is o PC <-[PC] + Carry out the actions specified by the instruction in the IR. The first two steps are termed as fetch step and the 3rd step is known as execution phase The fig shows an organization of the data path inside a processor with a single bus. The bus is internal to the processor that connects the processor to the memory and IO devices The data and address lines of the external memory are connected to the internal processor bus via the memory data register (MDR) and the memory address register (MAR). The registers MDR has two inputs and two outputs. Data may be loaded into MDR either from the memory bus or from the internal process bus. The data stored in MDR may be placed on either bus.
Some register are dedicated as special purpose register such as index register, stack pointers, accumulator etc. for example in the diagram y, z, temp are used by the programmer for any instruction. The multiplexer MUX selects either the output of register Y or a constant value to be provided as input A of the AW.The constant 4 is used to increment the contents of the program counter. As instruction execution progresses, data are transferred from one register to other of the ten passing through the ALU to perform some arithmetic or logical operation. The instruction decoder and control logic unit is responsible for implementing the actions specified by the instruction loaded in the IR register. The registers, ALU and inter connecting bus are collectively referred to as the data path. The sequence of execution of instruction is as follows: Transfer a word of data from one processor register to another or to the ALU. Perform arithmetic or a logic operation and store the result in a processor register Fetch the contents of a given memory location and load them into a processor register Store a word of data from a processor register into a given memory location. Some of the operations performed while executing an instruction are:
- Register transfer
- Arithmetic or logic operation
- Fetching a word from memory
- Storing a word in memory Register transfer: Instruction execution will be faster if the operands are stored in registers. During execution of an instruction data may be transferred from one register to another. The registers are connected to the bus via switches controlled by the signals Riin and Riout, when Riin is set to 1, the data on the bus are loaded into Ri are placed on the bus. The data transfer from R1 to R2 is done as follows: Enable R1out by setting it to 1. The content of R1 is now available on the processor internal bus. Enable R2in by setting H to 1. This loads data from the processor bus in to R2. Depending on the operations to be done, the control signals associated with the registers are asserted at the start of the clock cycle, as the flip-flops that the resistors are edge triggered. When edge triggered flip-flops are not used, two or more clock signals may be needed to guarantee proper transfer of data. This is called multiphase clocking.
The instruction MOV R1, R2 is done as follows.
3. Z out, R3 in. [At any point of time.]
To fetch a word from memory, the processor has to specify the address of the memory location where this information is stored and request a read operation. The processor transfers the required address to MAR, where o/p is connected to the address lines of the memory bus. The requested data from the memory is stored in registers MDR, form where they are transferred to other registers in the processor. MDR inE and MDR outE control the connection to the external bus During memory read and write operation, the timing of internal. Processor operations must be coordinated with the response of the addressed device on the memory bus. The processor completes one internal data transfer in one clock cycles. Example: To perform read operation, consider the instruction move R1, R2. This instruction execution is given as follows.
- MAR<-[R1]
- Start a read operation on the memory bus.
- Wait for the control signal called memory function completed (MFC)
- Load MDR from the memory bus.
- R2<-MDR. The control signals is being activated as follows for the above instruction
- R1 Out, MAR, read.
- MDRin E, WMFC (wait for memory function complete)
- MDRout, R2 in
The sum is stored in register Z and transferred to R1 in step 7. The End signal causes a new instruction fetch cycle to begin by returning to step 1. Branch instruction: A branch instruction replaces the contents of the PC with the branch target address. This address is usually obtained by adding an offset X, which is given in branch instruction. There are two types of branch
- Unconditional branch
- Conditional branch Control sequence for an unconditional branch instruction: The steps 1 to 3 constitute the fetch phase and it ends when the instructions is loaded into the IR in step3. Since the value of updated PC is already available in register Y, the offset X is gated onto the bus in step 4. The result which is the branch target address is loaded into the PC in step5. For the conditional branch: The ststus of the condition codes must be checked before loading a new value into thw PC. The step 4 in the above control sequence must be replaced with Offset-field. Thus if N=0 the processor returns to step 1 immediately after step 4. If N=1 step 5 is performed to execute branch instruction. 3. Explain multiple bus organization in detail. OR Explain the execution of a three operand instruction using multiple bus organization(April 2015) Multiple bus organization It shows the three bus structure used to connect the registers and the ALU of a processor. Using 3-bus structure we can reduce the number of steps needed. All the general purpose registers are combined into a single block called the register file. The register file is said to have 3 ports. There are 2 ports allowing the contents of 2 different registers to be accessed simultaneously and have their contents placed on the buses A and B .The third port allows the data on bus C to the loaded into a third register during the same clock cycle. FEATURES: Buses A and B are used to transfer the source operand to the A and B input of the ALU ,Where an narithmetic or logic operation may be performed. The result is transferred to the destination over bus C. If needed, the ALU may simply pass one of its 2 input operands unmodified to bus C. We will call the ALU control signals for such an operation R = A or R = B. A second feature is the introduction of the incriminator unit, Which is used to increment the PC by A. Using the incriminator eliminates the need to add 4 to the PC using the main ALU as was done in the figure. The source of the constant 4 at the ALU input multiplier is still useful. It can be used to increment other addresses, such as memory addresses in load/multiple and store multiple instruction.
Fig:THREE – BUS ORGANISATION OF THE DATA PATH Consider the 3 operand instruction ADD R4,R5,R6. The control sequence for executing this instruction is STEP ACTION 1 PCout, R = B, MARin, Read, IncPC 2 WMFc 3 MDRout B,R = B,IRin 4 R4out,R5 out B,Select A,ADD,R6in,END STEP 1: The contents of PC are passes through the ALU , using R = B control signal, and loaded into the MAR to start a memory read operation. At the same time the PC is incremented by 4.The value is loaded into MAR is the original contents of the PC. The incremented value is loaded into the PC at the end of the clock cycle and will not effect the contents of the MAR. STEP 2:The processor waits for MFC and loads the data received into MDR, then transfers them into IR.
