ECE 3550 DIGITAL DESIGN
FALL 2008
Project Assignment #1
(Team Project)
Total: 40 pts. (10 % of the course grade)
Due 4:00pm, Tuesday, October 21, 2008
Design, simulate, build, and demonstrate the correct operation of the serial data
processing module specified below. A functional block diagram is given on Page 2.
Use one Xilinx Spartan3E FPGA chip (the one that is mounted on your Xilinx Nexys 2
Board), as well as off-the-shelf ICs and other parts (as needed). Input signals are to be
driven by micro switches, output signals are to be displayed by Bar-LED Units. Pay
attention to the control of the bi-directional I/O Port of the ‘HC299 Shift Register: after
an operand has been loaded into the shift register the micro switches should be
electronically separated from the port (by means of a Three-State buffer chip) to allow
displaying the contents of the shift register. You may assume that the input signals to the
system are properly synchronized with respect to the CLK signal (i.e., you will set/reset
them that way). Make sure that your CLK signal will be bounce-free.You are to
provide for your own Nexys 2 Board,Circuit Bread Board and electronic parts,
respectively.
Description of Operation
Initially, signal DONE (output) is asserted (High), signal OVF (arithmetic overflow,
output) is deasserted (Low), signal outputs OP_LD (Operand Load) and RES_LD
(Result Load) are also deasserted (Low). Signal START (input) should be in deasserted
(Low) state. The two shift registers must be in Hold Mode, i.e., their contents are being
displayed on Bar-LED modules and the image won’t change while a train of clock pulses
is received.
In order to begin with a new arithmetic operation, the user should set up the two
operands (Operand_1 and Operand_2 in 8-bit,in2’s complement representation)
using DIP Switches and then assert the START signal. In response, the System
Controller (SC) should deassert DONE, and assert OP_LD.While OP_LD is high,the
SC should first load in parallel (broadside) the two operands into the associated shift
registers (‘HC299 Universal Shift Register with 3-State Outputs, or compatible part).
After the parallel load is executed the SC should control the shifting of the two operands
from the shift registers into temporary storage registers on the Spartan3E chip by
placing the shift registers in Shift Right Mode. At any time during the load process
signal START should be deasserted by the user. After the two operands are moved into
the storage registers signal OP_LD should be deasserted by the SC.
After the two operands are secured in their storage registers the arithmetic operation
should performed as follows: RES = (Operand_2 – Operand_1) signed-divided by 8,
where Operand_1 stands for the data received from Shift Register #1, Operand_2
stands for the data received from Shift Register #2 and RES stands for the result in 8-bit,
2’s complement representation. The SC should then shift out the bits of RES into
Shift Register #1 and simultaneously assert signal RES_LD. When the shift out
operation is concluded RES_LD should be deasserted and DONE should be asserted.
