VHDL Coding Basics
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Understanding If Statements, Port Modes, and Signal Assignment in VHDL Components, Slides of Computer Science
An introduction to vhdl programming, focusing on if statements, port modes, and signal assignment in vhdl components. It covers the definition of if statements in process statements, the sensitivity list of processes, and the modes of ports in vhdl. The document also explains how to describe the assignment of values to signals using signal assignment statements. Examples of vhdl components, such as half-adders, are provided to illustrate the concepts.
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2012/2013
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VHDL Coding Basics
Overview
Chip
Data Types
bit values: '0', '1' boolean values: TRUE, FALSE integer values: -(231) to +(231 - 1)
std_logic values: 'U','X','1','0','Z','W','H','L','-'
U' = uninitialized
'X' = unknown
'W' = weak 'X‘
'Z' = floating
'H'/'L' = weak '1'/'0‘
'-' = don't care
Std_logic_vector (n downto 0); Std_logic_vector (0 upto n);
Entity
Define inputs and outputs
Example:
Entity test is
Port( A,B,C,D: in std_logic;
E: out std_logic);
End test;
Inputs and Outputs
Chip
A
B
C
D
E
VHDL features
Case insensitive inputa, INPUTA and InputA are refer to same variable Comments ‘--’ until end of line If you want to comment multiple lines, ‘--’ need to be put at the beginning of every single line Statements are terminated by ‘;’ Signal assignment: ‘<=’ User defined names: letters, numbers, underscores (‘_’) start with a letter
VHDL structure
Library
Definitions, constants
Entity
Interface
Architecture
Implementation, function
VHDL - Entity
It is the interface for communication among different modules / components and define the signal port modes (INPUT and OUTPUT)
Output 1 Output 2
Output n
Input 1 Input 2
Input n
…... …...
Entity name
This is a black box that implemented by the statements in Architecture
VHDL - Entity
Define INPUT, OUTPUT Port
entity test7 is port ( inputa : in std_logic; inputb : in std_logic; output : out std_logic ); end test7;
Entity name should be same as the file name
DO NOT have ; here
Design using VHDL
Define the logic function
output <= inputa and inputb;
output is assigned to be inputa AND inputb
LHS contains only 1 variable only
RHS can be logics operations for many variables
Signal
All internal variables
Signal X,Y : std_logic;
Chip
Signal
A
B
C
D
X E
Y
Port Map
Chip1 : Chip_A
Port map (A,B,C,X,Y);
Chip2 : Chip_B
Port map (X,Y,D,E);
Chip_A
A
B
C D
Chip_B E
X
Y
Final code
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TEST IS PORT (A,B,C,D : IN STD_LOGIC; E : OUT STD_LOGIC); END TEST;
ARCHITECTURE BEHAVIOR OF TEST IS
SIGNAL X,Y : STD_LOGIC;
COMPONENT Chip_A PORT (L,M,N : IN STD_LOGIC; O,P : OUT STD_LOGIC); END COMPONENT;
COMPONENT Chip_B PORT (Q,R,S : IN STD_LOGIC; T : OUT STD_LOGIC); END COMPONENT;
BEGIN Chip1 : Chip_A PORT MAP (A,B,C,X,Y); Chip2 : Chip_B PORT MAP (X,Y,D,E);
END BEHAVIOR;
If Statement
If condition then
sequence_of_statements
End if;
If condition then
sequence_of_statements
Elsif condition then
sequence_of_statements
End if;
Example If A = ‘0’ then C<=B; End if;
If A = ‘0’ then C<=B; Elsif A = ‘1’ then C<=A; End if;