MULT Instruction - High Performance Computing - Lecture Slides, Slides of Computer Science

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High Performance Computing

Lecture 6

2

MULT Instruction

 Example: MULT R1, R

 MIPS 1 Solution: Put the 32 least significant

bits of the product in LO and the rest in HI

 For DIV: quotient in LO, remainder in HI

R1 R

The product could be twice as large (i.e., 64b) It may not fit into a single general purpose register 32 bits (^) 32 bits

4

Control Transfer Instructions

R31  PC + 8

PC  R

Jump and JAL, JALR JALR R Link System call SYSCALL SYSCALL

PC 

(PC)

31 - 28 || target 26

J target 26 Jump J, JR If R2 < 0, PC  PC + 4 - 16

BEQ, BNE, BLTZ R2, - 16

BGEZ, BLEZ,

BLTZ, BGTZ

Conditional Branch Mnemonics Example Meaning

5

Conditional Branch Instructions

Example: BEQ R1, R2, - 16

 Take the branch if contents of R1 = = contents of R  The target address of the branch is specified using PC relative addressing mode  PC + 4 - 16  For examples, we will use a more readable notation BEQ R1, R2, label If R2 < 0, PC  PC + 4 - 16

BEQ, BNE, BLTZ R2, - 16

BGEZ, BLEZ,

BLTZ, BGTZ

Conditional Branch Mnemonics Example Meaning

7

Jump and Link Instructions

R31  PC + 8

PC  R

JALR R

JAL target 26 Jump and JAL, JALR Link Mnemonics Example Meaning

 Unconditional control transfer to the instruction at the

target address along with remembering of PC+8 in R

 Target address specified as in J, JR instructions  We will see how this instruction is useful in function calls

8

C Control Transfer Constructs…

LW R1, X

loophead: loopbody BEQ R1, R0, loophead repeat loopbody until ( X != 0)

LW R1, X

BGTZ R1, thenpart elsepart: : thenpart: if (X > 0) thenpart; else elsepart goto label J label C MIPS 1 Instructions

10

 Warning about Load instructions

Interesting Notes from ISA Manual.

LW R1, - 8(R2)

ADD R3, R1, R

11

Interesting Notes from ISA Manual

 For load instructions: the loaded value might

not be available in the destination register for

use by the instruction immediately following

the load

 LOAD DELAY SLOT

 For control transfer instructions: the transfer

of control takes place only following the

instruction immediately after the control

transfer instruction

 BRANCH DELAY SLOT

13

Interesting Notes from ISA Manual

 For load instructions: the loaded value might

not be available in the destination register for

use by the instruction immediately following

the load

 LOAD DELAY SLOT

 For control transfer instructions: the transfer

of control takes place only following the

instruction immediately after the control

transfer instruction

 BRANCH DELAY SLOT

14

 Warning about Load instructions

 Warning about Control Transfer Instructions

Interesting Notes from ISA Manual.

LW R1, - 8(R2)

ADD R3, R1, R

LW R1, - 8(R2)

ADD R3, R1, R

An instruction that does not use R head: loopbody BEQ R1, R0, head head: loopbody BEQ R1, R0, head next-instruction

16 Opcode 6 bits Src 5 bits Constant 16 bits Dest 5 bits I Format Example: addi R 1, R 2, 8 lw R 1, 24 (R 2) bltz R 1, loop

MIPS 1 Instruction Encoding

17 Opcode 6 bits Jump address 26 bits J Format Example: jal fact

MIPS 1 Instruction Encoding

19

Steps in gcc

program.c cpp Library files cc as ld hello.s program.o a.out e.g., math.o, the math library These are text files – you can read or write them with a text editor These are object files (binary) – you can write programs to read them