Pipeline Hazards - High Performance Computing - Lecture Slides, Slides of Computer Science

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High Performance Computing

Lecture 23

2

Problem: Pipeline Hazards

A situation where an instruction cannot

proceed through the pipeline as it should

1. Structural hazard: When 2 or more

instructions in the pipeline need to use the

same resource at the same time

2. Data hazard: When an instruction depends

on the data result of a prior instruction that

is still in the pipeline

3. Control hazard: A hazard that arises due to

control transfer instructions

4

Solving Data Hazards

1. Interlock: Hardware that is included in the

processor to detect such a data dependency

and stall the dependent instruction

time

inst 0 1 2 3 4 5 6

Add IF ID EX MEM WB

Sub IF stall stall ID EX MEM

Or stall stall IF ID EX

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1. Interlocks & stalling dependent instructions

add R3, R1, R IF ID EX MEM WB or R7, R3, R IF ID EX sub R5, R3, R IF ID EX MEM

Solving Data Hazards

The result is available at the output of the ALU now (in the special purpose register ALUout)

7

Modified Processor Datapath

Imm

NPC

ALU Mem EXE (^) MEM

B

A

8

But Forwarding is Not Always Possible

LW R3, - 4(R1)

IF ID EX MEM WB

OR R7, R3, R

IF ID EX

SUB R5, R3, R

IF ID EX MEM

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Recall: Notes from ISA Manual.

 For load instructions: the loaded value might

not be available in the destination register for

use by the instruction immediately following

the load

 LOAD DELAY SLOT

 For control transfer instructions: the transfer

of control takes place only following the

instruction immediately after the control

transfer instruction

 BRANCH DELAY SLOT

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Solving Data Hazards

1. Interlocks & stalling dependent instructions

2. Forwarding or Bypassing

3. Load delay slot

4. Instruction Scheduling

 Reorder the instructions of the program so that

dependent instructions are far enough apart

 This could be done either

 by the compiler, before the program runs: Static Instruction Scheduling  by the hardware, when the program is running: Dynamic Instruction Scheduling