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Main points of this past exam are: Simple Transistor Structure, Structure, Process Sequence, Aluminum, Important Features, Lithography Steps, Masking Step
Typology: Exams
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Midterm Exam #1 Solutions EE143, Fall F Problem 1
(a) Cross-section along B-B’
(b) Cross-section along C-C’
(c ) Mask 1 – LOCOS patterning to define active device area Mask 2 - Poly gate patterning Mask 3 – contact hole opening through oxide Mask 4 – Al metal patterning
This process sequence needs 4 lithography steps. [Note: the source and drain is fabricated by a blanket implant using poly-gate as the blocking pattern. No need for an additional mask to form S/D doping].
(d ) No. There is an implantation annealing step at ~900C after S/D implant. If the Al gate is present, it will be molten.
Problem 2
(a)
p (channel stop)
SiO (FOX)
Gate oxide Al
p (channel stop)
Poly-Si
p (channel stop)
SiO (FOX)
Gate oxide Al
p (channel stop) p (channel stop)
SiO (FOX)
Gate oxide Al
p (channel stop)
Poly-Si
p (channel stop)
CVD SiO
SiO (FOX)
Al
p (channel stop)
n+
CVD SiO
p (channel stop)
CVD SiO
SiO (FOX)
Al
p (channel stop)
n+
CVD SiO
Thin Si3N4 as oxidation mask
SiO2 ∆
Thin Si3N4 as oxidation mask
SiO2^ ∆∆
(b)
d xox dt =^
A+2xox
From 0.48 =
and 0.266 =
, we get
A=0.243 μm , B= 0.597 μ m^2 /hour and B/A = 2.46 μ m/hour
(c) The oxidation rate goes up with gas pressure ( ∝ to P) (i) For a given needed oxide thickness , the oxidation time can be shorter. Therefore, higher throughput. (ii) For a given needed oxide thickness and same oxidation time, a lower oxidation temperature can be used. This will minimize mechanical stress generated by the difference in thermal expansion/contraction between oxide and Si. Less crystalline defects are expected.
(iii) For a given needed oxide thickness and same oxidation time, a lower oxidation temperature can be used. This will minimize dopant redistribution during the high-temperature oxidation cycle.
( d) Mobile ion charges – use HCl during oxidation to neutralize the mobile K+ or Na+ ions Interface charges near and at oxide interface – anneal in forming gas after metallization step to passivate broken bonds with hydrogen. Trapped oxide charge – mainly due to device operation or radiation damage.
Problem 3 (i) From range curves, phosphorus ion energy ~ 150 keV to create Rp = 0.2 μm.
The corresponding straggle ∆Rp is 0.065 μm. (ii)
Cmax exp[
Cmax =
φ 2.5∆Rp ⇒ φ = 1.85 × 10 13 /cm^2
(iii) RS of full gaussina profile’s is equivalent to two RS of haf-gaussians in parallel.
Note the equivalent x (^) j is now only 0.2 μm for these half-gaussians.
Using the n-type Gaussian Irvin curve with Co = 1.14 × 10 18 /cm^3 and N (^) B = 10 16
RS x (^) j = 450 ohm-μm or RS = 450/0.2 = 2250 ohm/square
Therefore , R (^) S of implant layer is 1125 ohm/square.
(iv) With a 7-degree tilt, the incoming ions will experience random scattering. A small fraction of the scattered ions will enter other crystallographic axes or planes. The channeling of these “lucky” ions will penetrate deeper than expected as compared with a truly random implantation depth profile, giving a small tail in the implant profile distribution. (v) The annealing step is to : (1) restore Si crystallinity by annealing out defects , and (2) place dopants into Si substituitional sites to make them electrically active.
Problem 4 ( a) Using Irvin curve with p-erfc profile ( p into n ) and N (^) B = 10 15 /cm^3 and Co = 3.9 × 10 20 /cm^3
Rs x (^) j = 20 Ω-μm
From C(x,t)=CS erfc(
x 2 Dt