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This is solution manual for Digital Logic Design course. It was helpful for assignment Dr. Archan Singh gave us at Punjab Engineering College. It includes: Present, state, Xilinx, Foundation, Series, software, HDL, IEEE, Logic, Architecture
Typology: Exercises
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5-24.
5-26.
T
C
T C T C T C
E
Y
Q (^8)
Q (^1)
Q (^2)
Q (^4)
Clock
Present state Next state FF Inputs
5-29. (All simulations performed using Xilinx Foundation Series software.)
5-33.
library IEEE; use IEEE.std_logic_1164.all;
entity reg_4_bit is port ( CLEAR, CLK: in STD_LOGIC; D: in STD_LOGIC_VECTOR (3 downto 0); Q: out STD_LOGIC_VECTOR (3 downto 0) ); end reg_4_bit;
architecture reg_4_bit_arch of reg_4_bit is begin
process (CLK, CLEAR) begin if CLEAR ='0' then --asynchronous RESET active Low Q <= "0000"; elsif (CLK'event and CLK='1') then --CLK rising edge Q <= D; end if; end process;
end reg_4_bit_arch;
library IEEE; use IEEE.std_logic_1164.all;
entity ripple_1_bit is port ( RESET, CLK, J, K: in STD_LOGIC; Q: out STD_LOGIC ); end ripple_1_bit;
architecture ripple_arch of ripple_1_bit is signal Q_out: std_logic; begin process (CLK, RESET) begin if RESET ='1' then -- asynchronous RESET active Low Q_out <= '0'; elsif (CLK'event and CLK='0') then --CLK falling edge if (J = '1' and K = '1') then Q_out <= not Q_out; elsif(J = '1' and K = '0') then Q_out <= '1'; elsif (J = '0' and K = '1') then Q_out <= '0'; end if; end if; end process; Q <= Q_out;
end ripple_arch;
-- (Continued in next column)
library IEEE; use IEEE.std_logic_1164.all;
entity ripple_4_bit is port ( RESET, CLK: in STD_LOGIC; Q: out STD_LOGIC_VECTOR (3 downto 0) ); end ripple_4_bit;
architecture ripple_4_bit_arch of ripple_4_bit is
component ripple_1_bit port ( RESET, CLK, J, K: in STD_LOGIC; Q: out STD_LOGIC ); end component ; signal logic_1: std_logic; signal Q_out: std_logic_vector(3 downto 0); begin bit0: ripple_1_bit port map(RESET, CLK, logic_1, logic_1, Q_out(0)); bit1: ripple_1_bit port map(RESET, Q_out(0), logic_1, logic_1, Q_out(1)); bit2: ripple_1_bit port map(RESET, Q_out(1), logic_1, logic_1, Q_out(2)); bit3: ripple_1_bit port map(RESET, Q_out(2), logic_1, logic_1, Q_out(3));
logic_1 <= '1'; Q <= Q_out;
end ripple_4_bit_arch;
