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7-3. Errata: Interchange statements “Transfer R1 to R2” and “Clear R2 synchronously with the clock.”
7-6.
7-9.
R1 R
Load Load Clock C
LOAD QQ 0 Q^12 Q 3
C
R 1
DD 0 D^12 D 3
LOAD QQ 0 Q^12 Q 3
C
R 2
DD 0 D^12 D 3
C 2 C 1 C (^0)
Clock
Load Q (^) (0-3) CO
CTR 4 Count C (^) (0-3) D (^) (0-3) CO
ADD 4 CI A(0-3) B(0-3)
Q (^) (0-3)
REG 4 D (^) (0-3)
0
CLK C C1 C R
R
a)
b) Q (^) (0-3)
REG 4 D (^) (0-3)
R
C (^) (0-3) CO
CIADD 4 A(0-3) B(0-3) Q (^) (0-3) REG 4 D (^) (0-3)
R
L
L
C
C
Clock
0101 1110 1100 0101 0100 0100 AND 1101 1111 OR 1001 1011 XOR
Problem Solutions – Chapter 7
7-11.
7-14.
7-19.
7-22.
7-24.
7-26.
sl 1001 1010 sr 0010 0110
R
a) Destination <- Source Registers R0 <- R1, R R1 <- R R2 <- R3, R R3 <- R R4 <- R0, R
b) Source Registers -> Destination R0 -> R R1 -> R0, R R2 -> R0, R R3 -> R R4 -> R1, R
c) The minimum number of buses needed for operation of the transfers is three since transfer Cb requires three different sources.
MUX
R1 R2 R3 R
MUX
MUX
d)
C = C 8 V = C 8 ⊕⊕⊕⊕ C 7 Z = N = F 7
F 7 + F 6 + F 5 + F 4 + F 3 + F 2 + F 1 + F 0
C (^) i X Y
FA
C (^) I + 1
X = A S1 + A S Y = B S1 S0 + B S (^1) G i
Ai
S S
S1S Bi
Bi
0
D D D D
B (^) i
a) XOR = 00, NAND = 01, NOR = 10 XNOR = 11 Out = S 1 A B + S 0 A B + S 1 A B + S 0 A B + S 1 S 0 A B b) The above is a simplest result.
(a) 1011 (b) 1010 (c) 0001 (d) 1100
