Download Logic Gates 1-Digital Logic Design-Solution Manual and more Exercises Digital Logic Design and Programming in PDF only on Docsity!
4-10.
4-12.
4-17.
J K Q(t) Q(t+1) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0
S R Q(t) Q(t+1) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 X 1 1 1 X
D Q(t) Q(t+1) 0 0 0 0 1 0 1 0 1 1 1 1
T Q(t) Q(t+1) 0 0 0 0 1 1 1 0 1 1 1 0
Q t ( + 1 ) = JQ + KQ Q t ( + 1 ) = S + RQ
Q t ( + 1 ) = D Q t (^^ +^1 )^ = T^ ⊕ Q
JA = B K (^) A = BX JB = X K (^) B = AX + AX
A(t+1) = JA A + K (^) A A = BA+ BA +XA B(t+1) = JB B + K (^) B B = X B + ABX + ABX
000
001 010
100 011
101
110
111
X = 1
X = 0
000
001 010
011
100 101
111 110
Present state Input Next state
A B C X A B B 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
State diagram is the combination of the above two diagrams.
Present state Input Next state Output
A B X A B Y 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1
0 1
2 3
1/1 (^) 0/
1/
0/
1/1 0/
0/ 1/
Format: X/Y
4-19.
4-20.
4-24.
4-25.
Present state Input Next state
A B X A B 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1
A
B
X
A
B
X
DA D B
DA = AB + AX + BX D B = AX + BX
0 1
10/
x1/x 00/ x1/x
00/ 10/
Present state Inputs Next state Output
Q(t) X Y Q(t+1) Z 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 X 1 X 1 X 0 X
Format: XY/Z (x = unspecified)
Present state Input Next state (^) Output
A B X A B Y 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 1 0 1 1 1 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0
A
B
X
A
B
X
DA D B
DA = AX + BX D B = BX + A X
A
B
X
Y
Y = A B
Present state Input Next state
A J K A 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 1 0 1 0
A
J
K
DA
DA = AJ+ AK
4-
4-40.
4-45.
library IEEE;
use IEEE.std_logic_1164.all;
entity mux_4to1 is
port (
S: in STD_LOGIC_VECTOR (1 downto 0);
D: in STD_LOGIC_VECTOR (3 downto
Y: out STD_LOGIC
end mux_4to1;
-- (continued in the next column)
architecture mux_4to1_arch of mux_4to1 is
begin
process (S, D)
begin
case S is
when "00" => Y <= D(0);
when "01" => Y <= D(1);
when "10" => Y <= D(2);
when "11" => Y <= D(3);
when others => null;
end case;
end process;
end mux_4to1_arch;
library IEEE;
use IEEE.std_logic_1164.all;
entity jkff is
port (
J,K,CLK: in STD_LOGIC;
Q: out STD_LOGIC
end jkff;
architecture jkff_arch of jkff is
signal q_out: std_logic;
begin
state_register: process (CLK)
begin
if CLK'event and CLK='0' then --CLK falling edge
-- (continued in the next column)
case J is
when '0' =>
if K = '1' then
q_out <= '0';
end if;
when '1' =>
if K = '0' then
q_out <= '1';
else
q_out <= not q_out;
end if;
when others => null;
end case;
end if;
end process;
Q <= q_out;
end jkff_arch;
module problem_4_45 (S, D, Y) ;
input [1:0] S ;
input [3:0] D ;
output Y;
reg Y ;
// (continued in the next column)
always @(S or D)
begin
if (S == 2'b00) Y <= D[0];
else if (S == 2'b01) Y <= D[1];
else if (S == 2'b10) Y <= D[2];
else Y <= D[3];
end
endmodule
4-47.
module JK_FF (J, K, CLK, Q) ;
input J, K, CLK ;
output Q;
reg Q;
// (continued in the next column)
always @(negedge CLK)
case (J)
0'b0: Q <= K? 0: Q;
1'b1: Q <= K? ~Q: 1;
endcase
endmodule
