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Chapter 3 Gates-Digital Logic Design-Solution Manual, Exercises of Digital Logic Design and Programming

Punjab Engineering CollegeDigital Logic Design and Programming

This is solution manual for Digital Logic Design course. It was helpful for assignment Dr. Archan Singh gave us at Punjab Engineering College. It includes: Time, Wave, Signals, Output, Gate, Level, Modeling, Digital, Design, Analysis

Typology: Exercises

2011/2012

Uploaded on 07/20/2012

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bg1
2
Problem Solutions – Chapter 3
3-11.
3-13.
3-15.
3-20.
A
B
C
D
11
111
1
F = AB + AC
A C A B A B A D A B D B C D A B C A C D A C D A C D A B C A B C A B D A B C D
a b c d e f g
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b = B + C D + CD c = B + C + D d = BCD + A + B D + BC + CD
e = B D + CD f = A + BD + BC + C D g = A + CD + BC + BC
XXXX
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XXXX
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XXXX
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a = A + C + BD + B D
V = D0 + D1 + D2 + D3
A0 = D1 + D0 D2
A1 = D0 D1
D3 D2 D1 D0 A1 A0 V
0000XX0
XXX1 0 0 1
XX10011
X100101
1000111 D0
D1
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D0
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A0 A1
X111
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Download Chapter 3 Gates-Digital Logic Design-Solution Manual and more Exercises Digital Logic Design and Programming in PDF only on Docsity!

3-11.

3-13.

3-15.

3-20.

A

B

C

D

F = AB + AC

A C A B A B A D A B D B C D A B C A C D A C D A C D A B C A B C A B D A B C D

a b c d e f g

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

b = B + C D + CD (^) c = B + C + D d = BCD + A + B D + BC + CD

e = B D + CD f = A + BD + BC + C D g = A + CD + BC + BC

X X X X

X X

X X X X

X X

X X X X

X X

X X X^ X

X X

X X X^ X

X X

X X X X

X X

X X^ X^ X

X X

a = A + C + BD + B D

V = D0 + D1 + D2 + D

A0 = D1 + D0 D

A1 = D0 D

D3 D2 D1 D0 A1 A0 V

0 0 0 0 X X 0

X X X 1 0 0 1

X X 1 0 0 1 1

X 1 0 0 1 0 1

1 0 0 0 1 1 1 D

D

D

D

D

D

D

D

A0 A

X X 1 1 1

3-25.

3-29.

3-35.

3-38.

3-41.

8/1 MUX D (^) (0-7) (^) Y 0 A(0-2)

8/1 MUX D (^) (0-6) (^) Y (^0)

A (^) (0-2)

D(0-7)

D(8-14) D (^) (7)

A(0-2)

A(3) 3 OR gates

4/1 MUX

0 1 2 3

A 0

Y

A 1

A B C D F A B C D F

D

1 0 0 0 0 CD

0 1 0 0 1 C D 1 1 0 0 1 +V

A B

+V

F

C D D C D

C 1 = T 3 + T 2 = T 1 C 0 + T 2 = A 0 B 0 C 0 + A 0 + B 0 = ( A 0 + B 0 ) C 0 + A 0 B 0 =( A 0 B 0 + C 0 ) ( A 0 + B 0 )

C 1 = A 0 B 0 + A 0 C 0 + B 0 C 0

S 0 = C 0 ⊕ T 4 = C 0 ⊕ T 1 T 2 = C 0 ⊕ A 0 B 0 ( A 0 + B 0 )= C 0 ⊕ ( A 0 + B 0 ) ( A 0 + B 0 )= C 0 ⊕ A 0 B 0 + A 0 B 0

S 0 = A 0 ⊕ B 0 ⊕ C 0

3-62.

3-66.

3-69.

3-72.

From 3-2: F = X Z + Z Y

Using Nand Gates:

signal T: std_logic_vector(0 to 2);

begin

g0: NOT1 port map (Y, T(0));

g1: NAND2 port map (X, Z, T(1));

g2: NAND2 port map (Z, T(0), T(2));

g3: NAND2 port map (T(1), T(2), F);

end

X

X

X

X

F

N N

N3 (^) N

N

N

3-76.

3-80.

//Fucntion F from problem 3-2 = X Z + Z Y

module cicuit_3_76(X, Y, Z, F);

input X, Y, Z;

output F;

assign F = (X & Z) | (Z & ~Y);

endmodule