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5-V Low-Drop Voltage Regulator TLE 4275
Features
- Output voltage 5 V ± 2%
- Very low current consumption
- Power-on and undervoltage reset
• Reset low down to V Q = 1 V
- Very low-drop voltage
- Short-circuit-proof
- Reverse polarity proof
- Suitable for use in automotive electronics
- ESD protection > 4 kV
- New type
Functional Description The TLE 4275 is a monolithic integrated low-drop voltage regulator in a 5 pin TO-package. An input
voltage up to 45 V is regulated to V Q,nom = 5.0 V. The IC
is able to drive loads up to 450 mA and is short-circuit proof. At overtemperature the TLE 4275 is turned off by the incorporated temperature protection. A reset
signal is generated for an output voltage V Q,rt of typ.
4.65 V. The delay time can be programmed by the external delay capacitor.
Type Ordering Code Package
- TLE 4275 D Q67006-A9354 P-TO252-5-1 (SMD)
- TLE 4275 G Q67006-A9343 P-TO263-5-1 (SMD)
- TLE 4275 Q67000-A9342 P-TO220-5-
- TLE 4275 S Q67000-A9442 P-TO220-5-
P-TO252-5-
P-TO263-5-
P-TO220-5-
P-TO220-5-
Dimensioning Information on External Components
The input capacitor C I is necessary for compensation of line influences. Using a resistor
of approx. 1 Ω in series with C I, the oscillating of input inductivity and input capacitance
can be damped. The output capacitor C Q is necessary for the stability of the regulation
circuit. Stability is guaranteed at values C Q ≥ 22 μF and an ESR of ≤ 5 Ω within the
operating temperature range.
Circuit Description
The control amplifier compares a reference voltage to a voltage that is proportional to the output voltage and drives the base of the series transistor via a buffer. Saturation control as a function of the load current prevents any oversaturation of the power element. The IC also incorporates a number of internal circuits for protection against:
- Overload
- Over-temperature
- Reverse polarity
Figure 2 Block Diagram
AEB
Buffer Reference
Bandgap
Protection Circuit
Control and
Temperature Saturation Sensor
Reset Generator
I Q
D RO
1 5
2
4
3
Note: Maximum ratings are absolute ratings; exceeding any one of these values may
cause irreversible damage to the integrated circuit.
Absolute Maximum Ratings
Parameter Symbol Limit Values Unit Test Condition
min. max.
Voltage Regulator
Input
Voltage V I – 42 45 V –
Current I I – – – Internally limited
Output
Voltage V Q – 1.0 16 V –
Current I Q – – – Internally limited
Reset Output
Voltage V RO – 0.3 25 V –
Current I RO – 5 5 mA –
Reset Delay
Voltage V D – 0.3 7 V –
Current I D – 2 2 mA –
Temperature
Junction temperature T j – 40 150 °C –
Storage temperature T stg – 50 150 °C –
Drop voltage 1)^ V dr – 250 500 mV I Q = 300 mA
V dr = V I – V Q
Load regulation ∆ V Q – 15 30 mV I Q = 5 mA to 400 mA
Line regulation ∆ V Q – 15 5 15 mV ∆ V l = 8 V to 32 V
I Q = 5 mA
Power supply ripple rejection
PSRR – 60 – dB f r = 100 Hz;
V r = 0.5 Vpp
Temperature output voltage drift
Reset Timing D and Output RO
Reset switching threshold
V Q,rt 4.5 4.65 4. 8 V –
Reset output low voltage
V ROL – 0.2 0.4 V R ext ≥ 5 kΩ;
V Q > 1 V
Reset output leakage current
I ROH – 0 10 μA V ROH = 5 V
Reset charging current I D,c 3.0 5.5 9.0 μA V D = 1 V
Upper timing threshold V DU 1.5 1. 8 2.2 V –
Lower timing threshold V DRL 0.2 0.4 0.7 V –
Reset delay time t rd 10 16 22 ms C D = 47 nF
Reset reaction time t rr – 0.5 2 μs C D = 47 nF
- (^) Measured when the output voltage V Q has dropped 100 mV from the nominal value obtained at V I = 13.5 V.
Characteristics (cont’d)
V I = 13.5 V; – 40 °C < T j < 150 °C (unless otherwise specified)
Parameter Symbol Limit Values Unit Measuring Condition
min. typ. max.
dV Q
dT
Figure 3 Test Circuit
Figure 4 Reset Timing
AES
V D I
C D 47 nF
GND
RO
5 kΩ
V Q
V RO
V D
I D, d
100 nF
C I (^) 2 1000 μF
C I 1
Q
22 μF
C Q R ext
1
4
5
3 2
I (^) I I Q
I RO
I GND
I D, c
I
AED
Thermal
t (^) rd
Power-on-Reset Voltage Dip Secondary Overload Spike at Output
V (^) Ι
dV = Ι D,c dt
V (^) Q VQ, rt
<t (^) rr
trr
at Input
Undervoltage Shutdown
C (^) D
t
V (^) RO
VD
t
t
t
V (^) DU
V (^) DRL
Current Consumption I q
versus Output Current I Q
Current Consumption I q
versus Output Current I Q
Drop Voltage V dr versus
Output Current I Q
Charge Current I D,c
versus Temperature T j
0 0
AED Ι (^) q
1
2
mA
3
= 13.5 V
mA
V Ι
20 40 60 80 120 ΙQ
0 0
AED Ι (^) q mA
= 13.5 V
mA
V Ι
100 200 300 400 600 ΙQ
10
20
30
40
50
60
70
80
AED
(^00) I Q
100
200
300
400
500
600
700
800 V mV dr
T j = 125 ˚C 25 ˚C
200 400 600 mA 1000
AED
(^0) -
V I = 13.5 V
1
2
3
4
5
6
7
8 μA
0 40 80 120 ˚C 160
I
T j
V D= 1 V
D, c I D, c
Delay Switching Threshold V DU, V DRL
versus Temperature T j
0
AED VDU V
= 13.5 V
˚C
V Ι
T j
0 40 80 120 160
VDU
VDRL
VDRL
A
(^8) ˚ max. 0.25 M A B 0.
Typical
9.8 ±0.
10 ±0.
8.5 1)
(15)
±0.
±0.3 1
0...0. 5x0.8 ±0.
1.27±0.
B
0.5 ±0.
±0. ±0.54.7 (^) 2.
All metal surfaces tin plated, except area of cut.
4x1.
P-TO263-5-1 (SMD)
(Plastic Transistor Single Outline)
GPT
_malac
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Dimensions in mm
gpt09064_ma
A
0.25 M A
Typical
9.8 ±0.
±0.
0...0.
0.8 ±0.
1.27±0.
0.05 ±0.
All metal surfaces tin plated, except area of cut.
C
±0. 17
±0.
8.5 1)
10 ±0.
3.7 (^) -0.
C
0.5 ±0.
±0. 8.6 10.
±0.
3.9±0. 8.4±0.
±0.
P-TO220-5-
(Plastic Transistor Single Outline)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mm
Edition 2001-04-
Published by Infineon Technologies AG i. Gr., St.-Martin-Strasse 53 D-81541 München © Infineon Technologies AG 1999 All Rights Reserved.
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