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Chapter 4 -- Modular Combinational Logic

L S B

M S B

D e c o d e r

n - t o - 2

n

x

x

y

y

x

n - 1

y

n

- 1

Decoders

C B A ( a ) ( b ) ( c ) m 0 = C B A m 1 = C B A m 2 = C B A m 3 = C B A m 5 = C B A m 4 = C B A m 6 = C B A m 7 = C B A B B A A m (^0) m (^1) m (^2) m (^3) m (^4) m (^5) m (^6) m (^7) C D B A L S B M S B k 0 k 1 k 2 k 3 m 0 m 4 m 8 m 1 2 2 - t o - 4 A A A A A A B B C C m 1 m 5 m 9 m 1 3 m 2 m 6 m 1 0 m 1 4 m 3 m 7 m 1 1 m 1 5 l 0 l 3 l 1 l^2 2 - t o - 4

More complex decoders

S.Isrie, MSc.

P X Q ( a ) ( b ) A B C f^ (^ Q^ ,^ X^ ,^ P^ ) 0 1 2 3 4 5 6 7 P X Q A B C f^ (^ Q^ ,^ X^ ,^ P^ ) 0 1 2 3 4 5 6 7

Example 4.1 -- Realize f(Q,X,P) =

 m (0,1,4,6,7) =  M (2,3,5)

A i n B i n K i n S W 1 S W 2 ( a ) ( b ) S i n g l e c h a n n e l A o u t B o u t K o u t B o u t K o u t A o u t a b k M u l t i p l e x e r D e m u l t i p l e x e r A i n B i n K i n a b k S i n g l e c h a n n e l

É É

K-Channel multiplexing/demultiplexing

Figure 4.

( a ) Y 4 - t o - 1 M u l t i p l e x e r Y B A B 0 0 1 1 A 0 1 0 1 ( b ) ( c ) 0 1 2 3 2 - t o - 4 D e c o d e r D (^0) D (^1) D (^2) D (^3) Y D (^0) D (^1) D (^2) D (^3) D (^0) D (^1) D (^2) D (^3) B A Y ( d ) D (^0) D (^1) D (^2) D (^3) B A S e l e c t i o n c o d e

Four-to-one multiplexer design

Half Adders

H A

( a )

( b )

( c )

x i y i

x i y i

c i s i

c i

s i

y i

x i

s i

c i

Figure 4.35 (a) -- (c)

Full Adders

( d ) ( e ) ( f ) ( g ) x (^) i y (^) i c (^) i - 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1 c (^) i s (^) i F A x (^) i y (^) i c (^) i s (^) i c (^) i - 1 s (^) i c (^) i c (^) i - 1 y (^) i x (^) i c (^) i - 1 y (^) i x (^) i s (^) i

S.Isrie, MSc. Figure 4.35 (d) -- (g)

Addition Time for a Basic Ripple-Carry Adder

Let t gate = the propogation delay through a typical logic gate

Half adder propagation delays

t add = 3 t gate

t carry = 2 t gate

Full adder propagation delays

t add = 3 t gate

t carry = 2 t gate

Ripple-Carry Adder ( n -bits)

t add = ( n - 1)2 t gate + 3 t gate

= (2 n + 1) t gate

SN7482 Two-Bit Pseudo Parallel Adder Module

A 2 B 2 S 2 G N D C 2 N C N C

A 2

B 2 S^2

S 1

A 1 B 1 C 0

( a )

S 1 A 1 B 1 V C C C 0 N C N C

C 2

Package Pin Configuration

SN7482 Pseudo Parallel Adder -- Logic Diagram

SN7482 Two-Bit Adder -- Logic Equations

C 1 = C 0 A 1 + C 0 B 1 + A 1 B 1 (4.20)

1 = C 0 C 1  + A 1 C 1  + B 1 C 1  + A 1 B 1 C 0

= C 1 ( C 0 + A 1 + B 1) + A 1 B 1 C 0

= ( C 0 + A 1 )( C 0 + B 1 )( A 1 + B 1 ) ( C 0 + A 1+ B 1) + A 1 B 1 C 0

= ( C 0 + A 1  B 1 )( A 1 + B 1 )( C 0 + A 1+ B 1) + A 1 B 1 C 0 (4.21)

= [ C 0 ( A 1+ B 1)+ C 0 A 1  B 1 ]( A 1 + B 1 )+ A 1 B 1 C 0

= C 0  A 1 B 1 + C 0  A 1  B 1+ C 0 A 1  B 1 + A 1 B 1 C 0

= C 0  A 1  B 1

Similarly

C 2 = C 1 A 2 + C 1 B 2 + A 2 B 2 (4.22)

2 = C 1  A 2  B 2

SN7483 Four-Bit Adder Module

B 4 S 4 C 4 C 0 G N D

V C C

B 1 A 1 S 1

S 3 A 3 S 2 B 2 A 2

( a )

A 4 B 3

S 4 C 4 C 0 B 1 A 1

S 3 A 3 B 3 S 2 B 2

S 1

A 4 A 2

B 4

Package Pin Configuration

SN7483 Four-Bit Adder Module -- Logic Diagram

• C
  • A
  • B
  • A
  • B - C - C
    • S - S
• B - S - C
• A
• B
• A
• B
• A
• B
• A
• C - P - S - C - P - S - C - P - S - C - P
  • C