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DRAWING
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
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Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
IV ALL RIGHTS RESERVED
II NOT TO REPRODUCE OR COPY IT
3
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BRANCH
DRAWING NUMBER SIZE D
SHEET
R
DATE
D
A
C
PAGE
A
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D
B
8 7 6 5 4 2 1
APPD
CK
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
DRAWING TITLE
REV ECN DESCRIPTION OF REVISION
REVISION
PROPRIETARY PROPERTY OF APPLE INC.
Schematic / PCB #’s
SCHEM,MLB_KEPLER,J45G
8/22/2013 DVT
1 OF 94
SCHEM,MLB,KEPLER,J45G
6 0002265654 ENGINEERING RELEASED 2013-08-
1 OF 119
dvt
6.0.
Debug Sensors
04/26/ 46 CLEAN_J
56
Load Side Voltage and Current Sensing
04/26/ 45 CLEAN_J
55
High Side Voltage and Current Sensing
04/26/ 44 CLEAN_J
54
SMBus Connections
04/26/ 43 CLEAN_J
53
SMC Project Support
04/26/ 42 CLEAN_J
52
SMC Shared Support
04/26/ 41 CLEAN_J
51
SMC
04/26/ 40 CLEAN_J
50
KEYBOARD/TRACKPAD (2 OF 2)
04/26/ 39 CLEAN_J
49
KEYBOARD/TRACKPAD (1 OF 2)
04/26/ 38 CLEAN_J
48
USB 3.0 CONNECTORS
04/26/ 37 CLEAN_J
46
Camera 2 of 2
04/26/ 36 CLEAN_J
40
Camera 1 of 2
04/26/ 35 CLEAN_J
39
SSD Connector
04/26/ 34 CLEAN_J
37
X29C CONNECTOR
04/26/ 33 CLEAN_J
35
Thunderbolt Connector B
04/26/ 32 CLEAN_J
33
Thunderbolt Connector A
04/26/ 31 CLEAN_J
32
Thunderbolt Mobile Support
04/26/ 30 CLEAN_J
30
Thunderbolt Host (2 of 2)
04/26/ 29 CLEAN_J
29
Thunderbolt Host (1 of 2)
04/26/ 28 CLEAN_J
28
DDR3 Termination
04/26/ 27 CLEAN_J
27
DDR3 SDRAM Bank B (2 OF 2)
04/26/ 26 CLEAN_J
26
DDR3 SDRAM Bank B (1 OF 2)
04/26/ 25 CLEAN_J
25
DDR3 SDRAM Bank A (2 OF 2)
04/26/ 24 CLEAN_J
24
DDR3 SDRAM Bank A (1 OF 2)
04/26/ 23 CLEAN_J
23
DDR3 VREF MARGINING
04/26/ 22 CLEAN_J
22
CPU Memory S3 Support
04/26/ 21 CLEAN_J
21
Project Chipset Support
04/26/ 20 CLEAN_J
20
Chipset Support
04/26/ 19 CLEAN_J
19
CPU & PCH XDP
04/26/ 18 CLEAN_J
18
PCH DECOUPLING
04/26/ 17 CLEAN_J
17
SYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/ PCH Grounds
04/26/ 16 CLEAN_J
16
PCH Power
04/26/ 15 CLEAN_J
15
PCH GPIO/MISC/NCTF
04/26/ 14 CLEAN_J
14
PCH PCI-E/USB
04/26/ 13 CLEAN_J
13
PCH DMI/FDI/PM/GFX/PCI
04/26/ 12 CLEAN_J
12
PCH RTC/HDA/JTAG/SATA/CLK
04/26/ 11 CLEAN_J
11
CPU Decoupling
05/02/ 10 CLEAN_J
10
CPU Ground
04/26/ 9 CLEAN_J
9
CPU Power
04/26/ 8 CLEAN_J
8
CPU DDR3 Interfaces
04/26/ 7 CLEAN_J
7
CPU Clock/Misc/JTAG/CFG
04/26/ 6 CLEAN_J
6
CPU DMI/PEG/FDI/RSVD
04/26/ 5 CLEAN_J
5
PD Parts
05/03/ 4 CLEAN_J
4
BOM Configuration
07/31/ 3 J15_REFERENCE
3
BOM Configuration
07/31/ 2 J15_REFERENCE
2
119 94 GPU (Kepler) Constraints
09/02/ SIDLE_J
118 93 Project Specific Constraints
04/26/ CLEAN_J
117 92 SMC Constraints
04/26/ CLEAN_J
116 91 Camera Constraints
04/26/ CLEAN_J
115 90 Thunderbolt Constraints
04/26/ CLEAN_J
114 89 Memory Constraints
04/26/ CLEAN_J
113 88 PCH Constraints 2
04/26/ CLEAN_J
112 87 PCH Constraints 1
04/26/ CLEAN_J
111 86 CPU Constraints
04/26/ CLEAN_J
110 85 PCB Rule Definitions
04/26/ CLEAN_J
105 84 NC & No Test
04/26/ CLEAN_J
104 83 Functional Test Points
04/26/ CLEAN_J
102 82 Signal Aliases
04/26/ CLEAN_J
100 81 Power Aliases
04/26/ CLEAN_J
97 80 eDP Muxed Graphics Support
08/14/ CLEAN_D
96 79 eDP Mux
07/31/ D2_MLB
95 78 RIO Connectors
04/26/ CLEAN_J
93 77 GFX IMVP VCore Regulator
07/31/ D2_MLB
92 76 KEPLER PEX PWR/GNDS
07/31/ D2_MLB
91 75 KEPLER GPIOS,CLK & STRAPS
07/31/ D2_MLB
90 74 KEPLER EDP/DP/GPIO
07/31/ D2_MLB
89 73 GDDR5 Frame Buffer B
07/31/ D2_MLB
88 72 GDDR5 Frame Buffer A
07/31/ D2_MLB
87 71 1V05 GPU / 1V35 FB POWER SUPPLY
07/31/ D2_MLB
86 70 KEPLER FRAME BUFFER I/F
07/31/ D2_MLB
85 69 KEPLER CORE/FB POWER
07/31/ D2_MLB
84 68 KEPLER PCI-E
07/31/ D2_MLB
83 67 eDP Display Connector
04/26/ CLEAN_J
82 66 Power Sequencing EG/PCH S
01/13/ D2_KEPLER
81 65 Power Control 1/ENABLE
06/23/ CLEAN_J
80 64 Power FETs
04/26/ CLEAN_J
78 63 Misc Power Supplies
04/26/ CLEAN_J
77 62 LCD/KBD Backlight Driver
04/26/ CLEAN_J
76 61 1V05V POWER SUPPLY
04/26/ CLEAN_J
75 60 5V / 3.3V Power Supply
04/26/ CLEAN_J
74 59 1.35V DDR3L SUPPLY
04/26/ CLEAN_J
73 58 CPU VR12.5 VCC Power Stage
04/26/ CLEAN_J
72 57 CPU VR12.5 VCC Regulator IC
04/26/ CLEAN_J
71 56 PBus Supply & Battery Charger
04/26/ CLEAN_J
70 55 DC-In & Battery Connectors
04/26/ CLEAN_J
66 54 AUDIO: JACK TRANSLATORS
04/26/ CLEAN_J
65 53 AUDIO: JACK
04/26/ CLEAN_J
64 52 AUDIO: SPEAKER AMP
04/26/ CLEAN_J
63 51 AUDIO:CODEC, DIGITAL
04/26/ CLEAN_J
62 50 AUDIO:CODEC, ANALOG
04/26/ CLEAN_J
61 49 SPI ROM / LPC+SPI Conn.
04/26/ CLEAN_J
60 48 Fan Connectors
06/23/ CLEAN_J
Contents
Date Sync
(.csa) Page 58 47 Thermal Sensors
04/26/ CLEAN_J
820-3787 1 PCBF,MLB_KEPLER,J45G PCB CRITICAL
051-0675 1 SCHEM,MLB_KEPLER,J45G SCH CRITICAL
ABBREV=ABBREVTITLE=MLB LAST_MODIFIED=Thu Aug 22 12:19:14 2013
Table of Contents
MASTER 1 MASTER
1
Contents
(.csa) Page
Date Sync
Apple Inc.
THEPROPRIETARY INFORMATION CONTAINED PROPERTY OF APPLE HEREIN INC. IS THE
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NOTICE OF PROPRIETARY PROPERTY:
PAGE
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SHEET IV ALL RIGHTS RESERVED
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REVISION
BRANCH
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
BOM NUMBER BOM NAME BOM OPTIONS
TABLE_BOMGROUP_HEAD
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BOM GROUP BOM OPTIONS
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PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
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J45G BOM Groups
BOM Variants
->
->
Development/Base BOM
DRAM SPD Straps
Module Parts
639-5248 PCBA,MLB,KEPLER,CRW_BEST,8G-MIC,VR-ELP,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_MICRON_1600_S,FB_2G_ELPIDA
639-5256 PCBA,MLB,KEPLER,CRW_BEST,16G-ELP,VR-ELP,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_ELPIDA_1600,FB_2G_ELPIDA
639-5257 PCBA,MLB,KEPLER,CRW_CTO,8G-HYN,VR-HYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_HYNIX_1600_S,FB_2G_HYNIX_A_DIE
639-5259 PCBA,MLB,KEPLER,CRW_CTO,8G-MIC,VR-HYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_MICRON_1600_S,FB_2G_HYNIX_A_DIE
639-5488 PCBA,MLB,KEPLER,CRW_CTO,16G-MIC,VR-4GHYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_MICRON_1600,FB_4G_HYNIX
639-5487 PCBA,MLB,KEPLER,CRW_CTO,16G-HYN,VR-4GHYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_HYNIX_1600,FB_4G_HYNIX
639-5486 PCBA,MLB,KEPLER,CRW_CTO,8G-ELP,VR-4GHYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_ELPIDA_1600_S,FB_4G_HYNIX
639-5485 PCBA,MLB,KEPLER,CRW_CTO,8G-MIC,VR-4GHYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_MICRON_1600_S,FB_4G_HYNIX
639-5484 PCBA,MLB,KEPLER,CRW_CTO,8G-HYN,VR-4GHYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_HYNIX_1600_S,FB_4G_HYNIX
639-5483 PCBA,MLB,KEPLER,CRW_BEST,16G-ELP,VR-4GHYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_ELPIDA_1600,FB_4G_HYNIX
639-5482 PCBA,MLB,KEPLER,CRW_BEST,16G-MIC,VR-4GHYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_MICRON_1600,FB_4G_HYNIX
639-5480 PCBA,MLB,KEPLER,CRW_BEST,8G-ELP,VR-4GHYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_ELPIDA_1600_S,FB_4G_HYNIX
639-5479 PCBA,MLB,KEPLER,CRW_BEST,8G-MIC,VR-4GHYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_MICRON_1600_S,FB_4G_HYNIX
639-5478 PCBA,MLB,KEPLER,CRW_BEST,8G-HYN,VR-4GHYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_HYNIX_1600_S,FB_4G_HYNIX
639-5268 PCBA,MLB,KEPLER,CRW_CTO,16G-ELP,VR-ELP,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_ELPIDA_1600,FB_2G_ELPIDA
333S0685 4 IC,SDRAM,GDDR5,64MX3,HYNIX,H5GC4H24MFP-T2C U8800,U8850,U8900,U8950 CRITICAL FB_4G_HYNIX
333S0734 4 IC,SDRAM,GDDR5,64MX3,HYNIX,H5GC2H24BFR-T2C U8800,U8850,U8900,U8950 CRITICAL FB_2G_HYNIX_29nm
333S0701 4 IC,SDRAM,GDDR5,2GBIT,5GBPS,170FBGA,EDW2032BBBG-6A-FU8800,U8850,U8900,U8950 CRITICAL FB_2G_ELPIDA_29nm
333S0695 4 IC,SDRAM,GDDR5,2GBIT,5GBPS,170FBGA U8800,U8850,U8900,U8950 CRITICAL FB_2G_ELPIDA
333S0630 4 IC,SDRAM,GDDR5,64MX32,A-DIE,HYNIX U8800,U8850,U8900,U8950 CRITICAL FB_2G_HYNIX_A_DIE
639-5267 PCBA,MLB,KEPLER,CRW_CTO,16G-ELP,VR-HYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_ELPIDA_1600,FB_2G_HYNIX_A_DIE
639-5266 PCBA,MLB,KEPLER,CRW_CTO,16G-MIC,VR-ELP,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_MICRON_1600,FB_2G_ELPIDA
639-5264PCBA,MLB,KEPLER,CRW_CTO,16G-HYN,VR-ELP,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_HYNIX_1600,FB_2G_ELPIDA
639-5261 PCBA,MLB,KEPLER,CRW_CTO,8G-ELP,VR-HYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_ELPIDA_1600_S,FB_2G_HYNIX_A_DIE
333S0631 4 IC,SDRAM,GDDR5,64MX32,D-DIE,SAMSUNG U8800,U8850,U8900,U8950 CRITICAL FB_2G_SAMSUNG
333S0667 32 IC,SDRAM,4GBIT,DDR3L-1600,HUMA,78P FBGA U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670 CRITICAL 4Gb_HYNIX_
333S0660 32 IC,SDRAM,4GBIT,DDR3L-1600,V80A,78P,FBGA U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670 CRITICAL 4Gb_MICRON_
333S0624 32 IC,SDRAM,DDR3-1600,512MX8,78FBGA,C-DIE,SAMSUNG U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670 CRITICAL 4Gb_SAMSUNG_
333S0667 16 IC,SDRAM,4GBIT,DDR3L-1600,HUMA,78P FBGA U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570 CRITICAL 4Gb_HYNIX_1600_S
639-5260 PCBA,MLB,KEPLER,CRW_CTO,8G-MIC,VR-ELP,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_MICRON_1600_S,FB_2G_ELPIDA
639-5263 PCBA,MLB,KEPLER,CRW_CTO,16G-HYN,VR-HYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_HYNIX_1600,FB_2G_HYNIX_A_DIE
RAM:2Gb_SAMSUNG_1600 RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H
RAM:2Gb_HYNIX_1600 RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L
RAM:2Gb_ELPIDA_1600 RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L
RAM:4Gb_HYNIX_1600_S 4Gb_HYNIX_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L
RAM:4Gb_SAMSUNG_1600_S 4Gb_SAMSUNG_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H
RAM:2Gb_MICRON_1600 RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H
RAM:4Gb_ELPIDA_1600_S 4Gb_ELPIDA_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L
RAM:4Gb_HYNIX_1600 4Gb_HYNIX_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L
RAM:4Gb_MICRON_1600 4Gb_MICRON_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H
RAM:4Gb_ELPIDA_1600 4Gb_ELPIDA_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L
RAM:4Gb_SAMSUNG_1600 4Gb_SAMSUNG_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H
RAM:4Gb_MICRON_1600_S 4Gb_MICRON_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H
685-0177 1 J45G MLB,KEPLER BASE BOM BASE CRITICAL BASE_BOM
985-0181 1 J45G MLB,KEPLER, DEVEL BOM DEVEL CRITICAL DEVEL_BOM
333S0700 1 IC,SDRAM,4GBIT,DDR3L-1600,GEMMA,96B FBGA U4000 CRITICAL
333S0624 16 IC,SDRAM,DDR3-1600,512MX8,78FBGA,C-DIE,SAMSUNG U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570 CRITICAL4Gb_SAMSUNG_1600_S
333S0703 16 IC,SDRAM,4GBIT,DDR3L-1600,F DIE,RS,78P U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570 CRITICAL 4Gb_ELPIDA_1600_S
333S0660 16 IC,SDRAM,4GBIT,DDR3L-1600,V80A,78P,FBGA U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570 CRITICAL 4Gb_MICRON_1600_S
333S0703 32 IC,SDRAM,4GBIT,DDR3L-1600,F DIE,RS,78P U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670 CRITICAL 4Gb_ELPIDA_
337S4256 1 IC,GPU,GK107-GT A2,BGA908 U8400 CRITICAL GK107:GT
337S4427 1 IC,GPU,107GX,926MHZ,1.0375V,1.5V,FBGA908 U8400 CRITICAL GK107:GX
337S4616 1 IC,GPU,CK107-762,A2,940MHz,5GBPS,1.2V,1.5V908BG U8400 CRITICAL GK107:GX
337S4599 1 IC,CPU,CRW,PRQ,C0,2.0,47W,4+3E,6M,BGA U0500 CRITICAL CPU_CRW:BETTER
XDP_DEBUG XDP_CONN,XDP_PCH
GFX_BM GK107:GX,DPMUX:HOCO
J45G_COMMON ALTERNATE,COMMON,J45G_COMMON1,J45G_COMMON2,J45G_PROGPARTS,GFX_BM,ACAPS:A
J45G_COMMON1 CPUMEM:S0,TBTHV:P15V,SKIP_5V3V3:AUDIBLE,CHGR_5V:LDO,CPUPEG:X8X8,S2_PWR:S
J45G_COMMON2 EDP:YES,LPCPLUS_CONN:YES,LPCPLUS_R:YES,XDP,RIO_PWR:1V5,SPI:DUAL_IO,SSD_PWR_EN:GPIO,CAM_WAKE:NO
J45G_PVT BKLT:PROD,SENSOR_NONPROD:N
J45G_PROGPARTS SMC_PROG:PROTO4,BOOTROM_PROG:PROTO4,TBTROM:PROG,TPAD_PSOC:PROG,GFX_PROGPARTS
GFX_PROGPARTS DPMUXMCU:PROG
J45G_DEVEL:ENG ALTERNATE,XDP_DEBUG,S0PGOOD_ISL,DDRVREF_DAC,SENSOR_NONPROD:Y,BKLT:ENG,DBGLED,CAM_XTAL:YES,DPMUX_DEBUG
J45G_DEVEL:DVT ALTERNATE,XDP_DEBUG,BKLT:PROD,SENSOR_NONPROD:N,DBGLED
337S4542 1 IC,PCH,LPT-M, HM87,C2,SR199,PRQ,20x20mm,FCBGA U1100 CRITICAL
338S1247 1 IC,TBT,FR-4C,A0,PRQ,CIO,SR1JC, FCBGA288 U2800 CRITICAL
338S1186 1 IC,BCM15700A2,S2 PCIE CMRA,8X8,208FCBGA U3900 CRITICAL
337S4624 1 IC,CPU,CRW,PRQ,C0,2.6,47W,4+3E,6M,BGA1364 U0500 CRITICAL CPU_CRW:CTO
639-5258 PCBA,MLB,KEPLER,CRW_CTO,8G-HYN,VR-ELP,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_HYNIX_1600_S,FB_2G_ELPIDA
639-5252 PCBA,MLB,KEPLER,CRW_BEST,16G-HYN,VR-ELP,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_HYNIX_1600,FB_2G_ELPIDA
639-5250 PCBA,MLB,KEPLER,CRW_BEST,8G-ELP,VR-ELP,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_ELPIDA_1600_S,FB_2G_ELPIDA
639-5249 PCBA,MLB,KEPLER,CRW_BEST,8G-ELP,VR-HYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_ELPIDA_1600_S,FB_2G_HYNIX_A_DIE
685-0177 COMMON PARTS,MLB,KEPLER,J
337S4600 1 IC,CPU,CRW,PRQ,C0,2.3,47W,4+3E,6M,BGA1364 U0500 CRITICAL CPU_CRW:BEST
639-5255 PCBA,MLB,KEPLER,CRW_BEST,16G-ELP,VR-HYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_ELPIDA_1600,FB_2G_HYNIX_A_DIE
639-5254 PCBA,MLB,KEPLER,CRW_BEST,16G-MIC,VR-ELP,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_MICRON_1600,FB_2G_ELPIDA
639-5253 PCBA,MLB,KEPLER,CRW_BEST,16G-MIC,VR-HYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_MICRON_1600,FB_2G_HYNIX_A_DIE
639-5251 PCBA,MLB,KEPLER,CRW_BEST,16G-HYN,VR-HYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_HYNIX_1600,FB_2G_HYNIX_A_DIE
639-5246 PCBA,MLB,KEPLER,CRW_BEST,8G-HYN,VR-ELP,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_HYNIX_1600_S,FB_2G_ELPIDA
985-0181 DEV,MLB,KEPLER,J
639-5489 PCBA,MLB,KEPLER,CRW_CTO,16G-ELP,VR-4GHYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_ELPIDA_1600,FB_4G_HYNIX
639-5481 PCBA,MLB,KEPLER,CRW_BEST,16G-HYN,VR-4GHYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_HYNIX_1600,FB_4G_HYNIX
639-5265 PCBA,MLB,KEPLER,CRW_CTO,16G-MIC,VR-HYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_MICRON_1600,FB_2G_HYNIX_A_DIE
639-5262 PCBA,MLB,KEPLER,CRW_CTO,8G-ELP,VR-ELP,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:4Gb_ELPIDA_1600_S,FB_2G_ELPIDA
639-5247 PCBA,MLB,KEPLER,CRW_BSET,8G-MIC,VR-HYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_MICRON_1600_S,FB_2G_HYNIX_A_DIE
639-5245 PCBA,MLB,KEPLER,CRW_BEST,8G-HYN,VR-HYN,J45G BASE_BOM,DEVEL_BOM,CPU_CRW:BEST,RAM:4Gb_HYNIX_1600_S,FB_2G_HYNIX_A_DIE
BOM Configuration
SYNC_MASTER=J15_REFERENCE SYNC_DATE=07/31/
J45G_COMMON
J45G_DEVEL:DVT
dvt
6.0.
2 OF 119
2 OF 94
WWW.AliSaler.Com
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
Apple Inc.
THEPROPRIETARY INFORMATION CONTAINED HEREIN IS THE PROPERTY OF APPLE INC.
B
D
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
D
A
C
PAGE TITLE
SHEET IV ALL RIGHTS RESERVED
R
D
DRAWING NUMBER SIZE
REVISION
BRANCH
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
APN 806-
APN 860-
APN 806-
SMT GND TEST PONTS
CPU BOSS APN 860-
APN 817-
APN 817-
APN 860-
J45 THERMAL MODULE STANDOFF
APN 860-
J45 STANDOFF
APN 870-
J45 POGO PINS
APN 806-
Thermal Module gaskets APN 875-
Frame Holes
PD parts
GPU BOSS APN 860-
APN 806-
APN 817-
STDOFF-4.5OD1.8H-SM
STDOFF-4.5OD1.9H-SM
2.8R2.
POGO-2.3OD-5.5H-SM-LOW-FORCE
SM
SL-1.1X0.45-1.4x0.
TH-NSP
SM
SHLD-MLB-USB-J
POGO-2.3OD-5.5H-SM-LOW-FORCE
SM
POGO-2.3OD-5.5H-SM-LOW-FORCE
SM
POGO-2.3OD-5.5H-SM-LOW-FORCE
SM
POGO-2.3OD-5.5H-SM-LOW-FORCE
SM
POGO-2.3OD-5.5H-SM-LOW-FORCE
SM
SL-1.1X0.45-1.4x0.
TH-NSP
SL-1.1X0.45-1.4x0.
TH-NSP
TH-NSP
SL-1.1X0.45-1.4x0.
TH-NSP
SL-1.1X0.45-1.4x0.
SL-1.1X0.45-1.4x0.
TH-NSP
SL-2.3X3.9-2.9X4.
TH-NSP
2.9OD1.2ID-1.35H-SM
2.9OD1.2ID-1.35H-SM
2.9OD1.2ID-1.35H-SM
2.9OD1.2ID-1.35H-SM
SMT-PAD-NSP
2.1SM2.0MM-CIR
SMT-PAD-NSP
2.1SM2.0MM-CIR 2.1SM2.0MM-CIR
SMT-PAD-NSP
MLB-MTG-BRKT-J5TH
SHLD-J45-CAN-FENCE2-MDP
SM^ SM
SHLD-J45-CAN-FENCE1-MDP
POGO-2.3OD-5.5H-SM-LOW-FORCE
SM
STDOFF-4.9OD2.38H-SM-
2.9OD1.2ID-1.35H-SM 2.9OD1.2ID-1.35H-SM
2.9OD1.2ID-1.35H-SM 2.9OD1.2ID-1.35H-SM 2.9OD1.2ID-1.35H-SM 2.9OD1.2ID-1.35H-SM
4.5OD1.85ID-1.95H
4.5OD1.85ID-1.95H
4.5OD1.85ID-1.95H
2.9OD1.2ID-1.35H-SM
5.0OD1.85ID-2.35H
5.0OD1.85ID-2.35H
5.0OD1.85ID-2.35H
5.0OD1.85ID-2.35H
6.0OD3.9H-SM
OMIT
OMIT
6.0OD3.9H-SM
OMIT
6.0OD3.9H-SM
OMIT
6.0OD3.9H-SM
946-3819 1 D2 MLB DYMAX ADHESIVE SEE-CURE 29993-SC
SYNC_MASTER=CLEAN_J45 SYNC_DATE=05/03/
PD Parts
GND_BATT_CHGND
GND_CHASSIS_MLBCAN
GND_CHASSIS_MLBCAN
GND_CHASSIS_MLBCAN
GND_CHASSIS_MLBCAN
GND_CHASSIS_MLBCAN
GND_CHASSIS_FAN
GND_CHASSIS_MLBCAN
EDGE_BOND CRITICAL
STDOFF-4.5OD1.8H-SM STDOFF-4.9OD2.38H-SM-SL-2.6X2NP-
4.5OD1.85ID-1.95H-
SH
1
SH
1
ZT
1
SH
1
SH
1
ZT 1
SH
1
SH
1
SH
1
SH
1
SH
1
SH
1
ZT 1
ZT 1
ZT 1
ZT 1 ZT 1
ZT 1
SH
1 2
SH
1 2
SH
1 2
SH
1 2
ZT
1
ZT
1
ZT
1
BR
1
SH
1 SH
1
SH
1
SH
1
SH
1
SH
1 2
SH
1 2
SH
1
2
SH
1 2
SH
1 2
SH
1
2
SH
1
SH
1
SH
1
SH
1 2
SH
1
SH
1
SH
1
SH
1
CG
1
CG
1
CG
1
CG
1
SH
1
dvt
051-
6.0.
4 OF 119
4 OF 94
WWW.AliSaler.Com
IN IN IN
IN
IN
IN
IN
IN
IN IN IN IN IN
OUT OUT OUT OUT OUT
OUT
OUT
OUT OUT OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT OUT OUT OUT
OUT
OUT
OUT OUT OUT OUT OUT
OUT
OUT
OUT
SYM 10 OF 12
EDP
DIGITAL
DISPLAY
INTERFACES
FDI
EDP_TXN
DDIC_TXP
FDI_TXP
FDI_TXN
FDI_TXP
FDI_TXN
EDP_DISP_UTIL
EDP_RCOMP
DDIB_TXN
DDIC_TXN
DDIC_TXP
DDIC_TXN
DDIB_TXN
DDIB_TXP
EDP_TXP
EDP_TXP
EDP_TXN
EDP_AUXP EDP_HPD
EDP_AUXN
DDID_TXP
DDID_TXN
DDID_TXP
DDID_TXN
DDID_TXP
DDID_TXN
DDID_TXP
DDID_TXN
DDIC_TXP DDIC_TXN
DDIC_TXN DDIC_TXP
DDIB_TXP DDIB_TXN DDIB_TXP DDIB_TXN
DDIB_TXP
RESERVED
SYM 12 OF 12
DAISY_CHAIN_NCTF
RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
DAISY_CHAIN_NCTF
TP
TP
TP
TP
TP
TP
TP
TP
NC
NC
NC
NC
NC
NC
NC
NC
IN IN IN IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
SYM 1 OF 12
FDI
PCI
EXPRESS BASED
INTERFACE SIGNALS
DMI
PEG_TX
PEG_TX
PEG_TX
PEG_TX
PEG_TX
PEG_TX
PEG_TX
PEG_TX
PEG_TX
PEG_TX
PEG_TX
PEG_TX
PEG_TX
PEG_TX
PEG_TX
PEG_TX
PEG_RX15*
PEG_RX14*
PEG_RX13*
PEG_RX12*
PEG_RX11*
PEG_RX10*
PEG_RX9*
PEG_RX8*
PEG_RX7*
PEG_RX6*
PEG_RX5*
PEG_RX4*
PEG_RX3*
PEG_RX2*
PEG_RX1*
PEG_RX0*
PEG_TX15*
PEG_TX14*
PEG_TX13*
PEG_TX12*
PEG_TX11*
PEG_TX10*
PEG_TX9*
PEG_TX8*
PEG_TX7*
PEG_TX6*
PEG_TX5*
PEG_TX4*
PEG_TX3*
PEG_TX2*
PEG_TX1*
PEG_TX0*
PEG_RCOMP
DISP_INT
FDI_CSYNC
PEG_RX PEG_RX PEG_RX PEG_RX PEG_RX PEG_RX PEG_RX PEG_RX PEG_RX PEG_RX PEG_RX PEG_RX PEG_RX PEG_RX PEG_RX PEG_RX
DMI_RX0* DMI_RX1* DMI_RX2* DMI_RX3*
DMI_RX
DMI_RX DMI_RX
DMI_TX0* DMI_TX1* DMI_TX2* DMI_TX3*
DMI_TX DMI_TX DMI_TX DMI_TX
DMI_RX
IN IN IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Apple Inc.
THEPROPRIETARY INFORMATION CONTAINED PROPERTY OF APPLE HEREIN INC. IS THE
8 7 5 4 2 1
B
D
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
D
AC
PAGE TITLE
SHEET IV ALL RIGHTS RESERVED
R
D
DRAWING NUMBER SIZE
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
exist between both TP’s on each corner.
daisy-chain fashion. Continuity should
Each corner of CPU has two testpoints.
Other corner test signals connected in
to match Intel symbol.
Port D pins out of order
NO_TEST NO_TEST
CPU Daisy-Chain Strategy:
82 82 82
82
82
82
82
82
82 82 82 82 82
82 82 82 82 82
82
82
82 82 82
82
82
82
82
82
82
82
82
82 82 82 82
82
82
82 82 82 82 82
82
82
82
HASWELL
OMIT_TABLE
BGA
1%1/16W MF-LF 402
10k
5% 1/16WMF-LF 402
HASWELL
OMIT_TABLE
BGA
TP-P
TP-P
TP-P
TP-P
TP-P
TP-P
TP-P
TP-P
8612 868412 868412 868412
868412
868412
8612
868412
8612
8612
868412
868412
868412
868412
868412
868412
402
1/16WMF-LF
1%
8612
8612
HASWELL
OMIT_TABLE
BGA
82 82 82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
CPU DMI/PEG/FDI/RSVD
SYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/
TP_DP_IG_A_MLP<3>
TP_DP_IG_A_MLN<3>
TP_DP_IG_A_MLP<2>
TP_DP_IG_A_MLN<2>
=PEG_D2R_N<2>
TRUE CPU_DC_BE53_BF
CPU_DC_A3_B3 TRUE
CPU_DC_A
TP_DP_IG_B_MLP<0>
PPVCOMP_S0_CPU
TP_DP_IG_A_MLP<1>
CPU_DC_BC
CPU_DC_A3_B3 TRUE
CPU_DC_BF
TRUE CPU_DC_B54_C
DMI_S2N_N<0>
=PEG_D2R_N<13>
=PEG_D2R_N<7>
CPU_EDP_RCOMP
TP_DP_IG_D_MLP<3>
PPVCCIO_S0_CPU
TP_DP_IG_A_AUXCHN
PPVCOMP_S0_CPU
=PEG_D2R_N<6>
=PEG_D2R_N<5>
=PEG_R2D_C_P<9>
CPU_PEG_RCOMP
=PEG_R2D_C_P<0>
=PEG_R2D_C_N<0>
DMI_N2S_N<2>
DMI_N2S_P<1>
DMI_N2S_N<3>
DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_P<3>
DMI_S2N_P<2>
=PEG_D2R_N<0>
=PEG_D2R_N<9>
DMI_S2N_N<2>
FDI_INT
FDI_CSYNC
=PEG_R2D_C_P<15>
=PEG_R2D_C_P<14>
=PEG_R2D_C_P<13>
=PEG_R2D_C_P<12>
=PEG_R2D_C_P<11>
=PEG_R2D_C_P<10>
=PEG_R2D_C_P<8>
=PEG_R2D_C_P<7>
=PEG_R2D_C_P<6>
=PEG_R2D_C_P<4>
=PEG_R2D_C_P<3>
=PEG_R2D_C_P<1>
=PEG_R2D_C_P<2>
=PEG_R2D_C_N<15>
=PEG_R2D_C_N<14>
=PEG_R2D_C_N<13>
=PEG_R2D_C_N<11>
=PEG_R2D_C_N<10>
=PEG_R2D_C_N<8>
=PEG_R2D_C_N<9>
=PEG_R2D_C_N<7>
=PEG_R2D_C_N<6>
=PEG_R2D_C_N<5>
=PEG_R2D_C_N<4>
=PEG_R2D_C_N<3>
=PEG_R2D_C_N<2>
=PEG_R2D_C_N<1>
=PEG_D2R_P<14>
=PEG_D2R_P<15>
=PEG_D2R_P<12>
=PEG_D2R_P<11>
=PEG_D2R_P<9>
=PEG_D2R_P<10>
=PEG_D2R_P<7>
=PEG_D2R_P<6>
=PEG_D2R_P<4>
=PEG_D2R_P<2>
=PEG_D2R_P<0>
=PEG_D2R_N<15>
=PEG_D2R_N<14>
=PEG_D2R_N<12>
=PEG_D2R_N<10>
=PEG_D2R_N<11>
=PEG_D2R_N<8>
=PEG_D2R_N<3>
=PEG_D2R_N<1>
DMI_S2N_P<1>
DMI_S2N_P<0>
DMI_S2N_N<3>
DMI_S2N_N<1>
DMI_S2N_P<3>
=PEG_R2D_C_P<5>
=PEG_D2R_P<1>
DMI_N2S_P<0>
DMI_N2S_P<2>
=PEG_D2R_N<4>
TP_DP_IG_A_MLN<0>
TP_DP_IG_C_MLP<2>
TP_EDP_DISP_UTIL
TP_DP_IG_B_MLN<0>
TP_DP_IG_C_MLN<1>
TP_DP_IG_C_MLP<0>
TP_DP_IG_C_MLN<0>
TP_DP_IG_B_MLN<3>
TP_DP_IG_B_MLP<2>
TP_DP_IG_A_MLP<0>
TP_DP_IG_A_MLN<1>
TP_DP_IG_D_MLN<1>
TP_DP_IG_D_MLP<0>
TP_DP_IG_D_MLN<3>
TP_DP_IG_D_MLP<2>
TP_DP_IG_D_MLN<2>
TP_DP_IG_C_MLP<1>
TP_DP_IG_C_MLN<2>
TP_DP_IG_C_MLN<3>
TP_DP_IG_C_MLP<3>
TP_DP_IG_B_MLN<1>
TP_DP_IG_B_MLP<1>
TP_DP_IG_B_MLN<2>
TP_DP_IG_B_MLP<3>
TP_DP_IG_A_AUXCHP
=PEG_D2R_P<3>
=PEG_D2R_P<5>
=PEG_D2R_P<8>
=PEG_D2R_P<13>
TP_DP_IG_D_MLP<1>
TP_DP_IG_D_MLN<0>
=PEG_R2D_C_N<12>
DP_IG_A_HPD_L
CPU_DC_A53_B53 TRUE
CPU_DC_A52_B52 TRUE
CPU_DC_B2_C3 TRUE
CPU_DC_A53_B53 TRUE
CPU_DC_A52_B52 TRUE
CPU_DC_BE3_BF3 TRUE
CPU_DC_BE2_BF2 TRUE
CPU_DC_BD54_BE54 TRUE
CPU_DC_BE2_BF2 TRUE
CPU_DC_BD1_BE1 TRUE
CPU_DC_BD54_BE54 TRUE
CPU_DC_BD1_BE1 TRUE
CPU_DC_B54_C54 TRUE
TRUE CPU_DC_BE52_BF
TRUE CPU_DC_C1_C
TRUE CPU_DC_C1_C
TRUE CPU_DC_B2_C
CPU_DC_BE52_BF52 TRUE
CPU_DC_BE3_BF3 TRUE
CPU_DC_D
CPU_DC_D
CPU_DC_A
CPU_DC_BF
CPU_DC_BC
CPU_DC_BE53_BF53 TRUE
(^1) R
2
AT40 U
F
AB
AB
AC
AC
AB
AB
AC AC
AF AF
AG
AG
AF AF
AG
AG
F
AH
AH
E C
M
V V V
Y
Y
B E D B
L
L
M
L
F D
M Y V V Y Y
A F C A M L M L
B C
T R R R T T
E D
G
E J
G
J J
C B
T R R R T T
D E
G
E J G J J
U
C
A
C
A
D
B
D
B
C
A
C
A
D
B
D
B
C
A
C
A
D
B
D
B
F F
E
E
AG
C A D B
C
A
D
B
(^1) R
2
(^1) R
2
U
AA
AA
A A A
B B
B B B
BC
BC BD
BD BE BE BE BE BE BE BF BF BF
BF BF BF
C C C
C D
D
AD
AE
AE
AF
AG
AN
AN
AN
G G
TP
1
TP
1
TP
1
TP
1
TP
1
TP
1
TP
1
TP0521 1
5 OF 94
5 OF 119
6.0.
051-
dvt
82
82
82
82
5
5
5 8
82
5 5
86
6 8 10 18 57
82
5 8
86
82
82
82
82 20
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5 5 5
5
5
5
OUT OUT
OUT
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
BI NC NC
BI BI BI BI BI BI BI BI BI BI BI BI BI
BI
BI
BI BI BI BI BI BI
BI
BI
BI BI BI BI BI BI
BI
BI
BI BI BI BI BI BI
BI
BI
BI BI BI BI BI BI
BI
BI
BI BI BI BI BI BI
BI
BI
BI BI BI BI BI BI
BI
BI
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
OUT OUT OUT OUT OUT
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
SYM 3 OF 12
MEMORY
CHANNEL A
SA_DQ
SA_DQ
SA_DQ
SA_DQ SA_DQ SA_DQ SA_DQ
SA_CKP
SA_CKN
SA_CKP
SA_CKP
SA_CKN
SA_CKP
SA_CKN
SA_CKE
SA_CS1*
SA_DQ
SM_VREF
SA_DQSN
SA_DQSN
SA_DQSN
SA_DQSN
SA_DQSN
SA_DQSN
SA_DQSN
SA_DQSN
SA_DQS
SA_DQS
SA_DQS SA_DQS
SA_DQS
SA_DQS
SA_DQS
SA_DQS
SA_MA
SA_MA
SA_MA
SA_MA
SA_MA
SA_MA
SA_MA SA_MA
SA_MA
SA_MA SA_MA
SA_MA SA_MA
SA_CAS*
SA_WE*
VSS_BC
SA_RAS*
SA_BS SA_BS
SA_ODT SA_BS
SA_ODT
SA_ODT
SA_ODT
SA_CS3*
SA_CS2*
SA_CS0*
SA_CKE
SA_CKE
SA_CKE
SA_DQ
SA_DQ SA_DQ SA_DQ
SA_DQ
SA_DQ SA_DQ SA_DQ SA_DQ SA_DQ SA_DQ SA_DQ
SA_DQ SA_DQ SA_DQ SA_DQ SA_DQ
SA_DQ SA_DQ SA_DQ SA_DQ SA_DQ SA_DQ SA_DQ SA_DQ SA_DQ SA_DQ SA_DQ SA_DQ SA_DQ SA_DQ
SA_DQ SA_DQ SA_DQ SA_DQ SA_DQ SA_DQ SA_DQ SA_DQ SA_DQ SA_DQ SA_DQ
SA_DQ SA_DQ SA_DQ
SA_DQ
SA_DQ
SA_DQ
SA_DQ
SA_DQ SA_DQ
SA_DQ
SA_DQ
SA_DQ
SB_DIMM_VREFDQ
SA_DIMM_VREFDQ
RSVD
RSVD
RSVD
RSVD
SA_CKN
SA_MA
SA_MA SA_MA
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
SA_DQ SA_DQ
RSVD
RSVD
SYM 4 OF 12
MEMORY
CHANNEL B
SB_DQ
SB_DQ
RSVD
SB_CKN
SB_CKE
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
SB_DQSN
SB_DQSN
SB_DQS SB_DQS
SB_DQS
SB_DQS SB_DQS
SB_DQ SB_DQ SB_DQ SB_DQ SB_DQ
SB_DQ SB_DQ SB_DQ SB_DQ SB_DQ SB_DQ SB_DQ SB_DQ7 SB_CKE SB_DQ SB_DQ SB_DQ10 (^) SB_CKE SB_DQ SB_DQ SB_DQ SB_DQ14 SB_CKE SB_DQ SB_DQ16 SB_CS0* SB_DQ17 SB_CS1* SB_DQ18 SB_CS2* SB_DQ19 SB_CS3* SB_DQ SB_DQ21 SB_ODT SB_DQ22 SB_ODT SB_DQ23 SB_ODT SB_DQ24 SB_ODT SB_DQ25 SB_BS SB_DQ26 SB_BS SB_DQ
SB_DQ SB_RAS* SB_WE* SB_CAS*
SB_MA SB_DQ36 SB_MA SB_DQ37 SB_MA SB_DQ38 SB_MA SB_DQ39 SB_MA SB_DQ40 SB_MA SB_MA SB_DQ41 (^) SB_MA SB_DQ42 (^) SB_MA SB_DQ43 (^) SB_MA SB_DQ44 (^) SB_MA SB_DQ SB_DQ46 SB_MA SB_DQ47 SB_MA SB_DQ48 SB_MA SB_MA SB_DQ49 (^) SB_MA SB_DQ SB_DQ51 (^) SB_DQSN SB_DQ52 (^) SB_DQSN SB_DQ SB_DQ54 SB_DQSN SB_DQ SB_DQ56 SB_DQSN SB_DQ57 SB_DQSN SB_DQ58 (^) SB_DQSN SB_DQ SB_DQ SB_DQ SB_DQ SB_DQ SB_DQS
SB_DQS SB_DQS
SB_CKP
SB_CKN SB_CKP
SB_CKN SB_CKP
SB_CKN SB_CKP
SB_BS
VSS_AU
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT OUT OUT
OUT
OUT
OUT
OUT OUT OUT OUT OUT OUT
OUT
OUT OUT
OUT
OUT OUT
OUT
OUT
OUT
OUT
OUT OUT OUT OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT OUT OUT
BI
BI
BI
BI
BI
BI
BI BI
BI
BI
BI
BI
BI
BI
BI BI
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Apple Inc.
THEPROPRIETARY INFORMATION CONTAINED PROPERTY OF APPLE HEREIN INC. IS THE
8 7 5 4 2 1
B
D
C
BA
NOTICE OF PROPRIETARY PROPERTY:
PAGE
D
A
C
PAGE TITLE
SHEET IV ALL RIGHTS RESERVED
R
D
DRAWING NUMBER SIZE
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
8622
8622
22
892423 892423 892423 892423 892423 892423 892423 892423 892423 892423 892423 892423 892423 892423
892423
892423
892423 892423 892423 892423 892423 892423
892423
892423
892423 892423 892423 892423 892423 892423
892423
892423
892423 892423 892423 892423 892423 892423
892423
892423
892423 892423 892423 892423 892423 892423
892423
892423
892423 892423 892423 892423 892423 892423
892423
892423
892423 892423 892423 892423 892423 892423
892423
892423
892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625 892625
23 27 89 23 27 89
24 27 89 24 27 89 24 27 89
23 24 27 89 23 24 27 89 23 24 27 89 23 24 27 89 23 24 27 89 23 24 27 89 23 24 27 89 23 24 27 89 23 24 27 89 23 24 27 89 23 24 27 89 23 24 27 89 23 24 27 89 23 24 27 89 23 24 27 89 23 24 27 89
OMIT_TABLE
HASWELL BGA
OMIT_TABLE
HASWELL BGA
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
23 24 89
24 27 89
23 27 89
24 27 89
23 27 89
23 27 89
23 24 27 89 23 24 27 89 23 24 27 89
23 24 27 89
23 24 27 89
23 24 27 89
25 27 89 25 27 89 25 27 89
26 27 89 26 27 89 26 27 89
25 27 89
25 26 27 89 25 26 27 89
26 27 89
25 27 89 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89 25 26 27 89 25 26 27 89 25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89
25 26 27 89 25 26 27 89 25 26 27 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89 25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89
25 26 89 25 26 89
SYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/
CPU DDR3 Interfaces
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_CS_L<1>
MEM_A_DQ<45>
MEM_A_DQ<54>
MEM_A_DQ<51>
MEM_A_DQ<53>
MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<52>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<61>
MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DQ<0>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<19>
MEM_B_DQ<17>
MEM_B_DQ<15>
MEM_B_DQ<20>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<25>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<31>
MEM_B_DQ<40>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<51>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<61>
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_A_DQ<60>
MEM_B_CLK_N<0>
MEM_B_CLK_P<0>
MEM_B_CKE<0>
MEM_B_CLK_N<1>
MEM_B_CLK_P<1>
MEM_B_CKE<1>
MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_B_ODT<0>
MEM_B_ODT<1>
MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BA<2>
MEM_B_RAS_L
MEM_B_WE_L
MEM_B_CAS_L
MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
MEM_A_CLK_N<0>
MEM_A_CLK_P<0>
MEM_A_CKE<0>
MEM_A_CLK_N<1>
MEM_A_CLK_P<1>
MEM_A_CKE<1>
MEM_A_CS_L<0>
MEM_A_ODT<0>
MEM_A_ODT<1>
MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BA<2>
MEM_A_RAS_L
MEM_A_WE_L
MEM_A_CAS_L
MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
MEM_B_DQS_N<7>
MEM_B_DQS_N<6>
MEM_B_DQS_N<5>
MEM_B_DQS_N<4>
MEM_B_DQS_N<3>
MEM_B_DQS_N<2>
MEM_B_DQS_N<1>
MEM_B_DQS_N<0>
MEM_B_DQS_P<5>
MEM_B_DQS_P<4>
MEM_B_DQS_P<3>
MEM_B_DQS_P<2>
MEM_B_DQS_P<1>
MEM_B_DQS_P<0>
MEM_A_DQS_N<7>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<4>
MEM_A_DQS_N<3>
MEM_A_DQS_N<2>
MEM_A_DQS_N<1>
MEM_A_DQS_N<0>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>
MEM_A_DQS_P<5>
MEM_A_DQS_P<4>
MEM_A_DQS_P<3>
MEM_A_DQS_P<2>
MEM_A_DQS_P<1>
MEM_A_DQS_P<0>
MEM_A_DQ<17>
MEM_A_DQ<14>
CPU_DIMMB_VREFDQ
CPU_DIMMA_VREFDQ
MEM_B_DQ<52>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_B_DQS_P<7>
MEM_B_DQS_P<6>
CPU_DIMM_VREFCA
MEM_B_DQ<16>
MEM_B_DQ<18>
U
AU
AU
AV
AV
AV
AW
AW
AY
AY
BA
BA
BC
BD
BC BD BD
BE
BE
BF
BC
BD
BE
BD
BE
BD
BF
BC
BF
BC
BE BC BE BD
AR
AH
AH
AR AR
AN
AN
AN
AR AR AV AV AY AY
AK
AV AV AY AY AY AY
BA
BA
AY AY
AK
BA
BA BF BC BC BF BE BD BD BE
AH
BC BE BE BC BD BF BE BD BB BC
AH
AW
AW
BB BB AW AW AU AU AR AR
AK
AU AU AR AR
AK
AN
AN
AJ
AP
AW BA BE BD BA
AT
AJ
AP
AW AY BD BE BA AT
BD BD
BD BF BC BE BE BE
BF BE BF BC BF BC BE BC
BC BF BF BD
BF BF
AN
AM
BC
U0500 AY
BC
BC
BD
BD
BD
BE
BE
BE BF
BF
AY BA BA
AV
AU
AU
AV
AV
AW
AW
BA
BA
AV
AV
AY
AY
BA AY AU AW
AC AC
AV AV AU AU AV AV BC BE BD BC
AE
BD BD BE BF BE BD BC BF BF BC
AE
BD BE BA AU BA AV AY AV AY AU
AC
AU AY BA AU AV BA AY AV AU BA
AC
AV BA AV AY AU AY
AM
AM
AK AK
AE
AM
AM AK AK
AE AU AU
AD
AV BE BE AW AW AW
AL
AD
AU BD BD AW AW AW
AL
BA AW
AU AY AW AU AW BA
AY AV AW AY AT AV BA AU
AY BA AV AW
AV AW
AU
dvt
051-
6.0.
7 OF 119
7 OF7 OF 9494
7 OF 119
6.0.
051-
dvt
BI
OUT
IN
SYM 5 OF 12
RSVD
VIDSOUT
VIDSCLK
VIDALERT*
RSVD79(VSS)
RSVD VSS_V50(RSVD)
VSS_AP50(RSVD)
VSS_AP49(RSVD)
VSS_AN49(RSVD)
VSS_AM50(RSVD)
IVR_ERROR
VSS_AK49(RSVD)
VSS_AJ49(RSVD)
VSS_AJ50(RSVD)
VSS_AG50(RSVD)
VSS_AD50(RSVD)
VSS_AB50(RSVD)
FC_F
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCC_L VCC_M
VCOMP_OUT
VCC_SENSE
VSS_B
FC_D FC_D
VDDQ
VCC
VCC
VCCIO_OUT
RSVD
RSVD
VSS_E
PWR_DEBUG
RSVD
SYM
6
OF 12 POWER
VCC
VCC
IN
OUT
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Apple Inc.
THEPROPRIETARY INFORMATION CONTAINED PROPERTY OF APPLE HEREIN INC. IS THE
BD
C
BA
NOTICE OF PROPRIETARY PROPERTY:
PAGE
D
AC
PAGE TITLE
SHEET IV ALL RIGHTS RESERVED
R
D
DRAWING NUMBER SIZE
REVISION
BRANCH
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Max load: 300mA
Connections would be required
for 2014 CPU support.
R0802.2:
R0800.2:
R0810.2:
Max load: 300mA
NOTE: Aliases not used on CPU supply outputs
to avoid any extraneous connections.
5% 1/16WMF-LF 402
8657
PLACE_NEAR=U0500.J50:2.54mm
402
1/16W
1% MF-LF
402
5% MF-LF1/16W
8657
PLACE_NEAR=U0500.J53:38mm
5% MF-LF 402 1/16W
8657
PLACE_NEAR=R0810.1:2.54mm
1% 1/16WMF-LF 402
OMIT_TABLE
HASWELL BGA
OMIT_TABLE^ HASWELL
BGA
18
PLACE_NEAR=U0500.C50:50.8mm
PLACE_SIDE=BOTTOM
1/16W MF-LF 402
5%
8657
CPU Power
SYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/
PPVCCIO_S0_CPU
MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V
CPU_VIDSOUT_R
CPU_VIDALERT_R_L
TP_CPU_IVR_ERROR
MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V
PPVCOMP_S0_CPU
CPU_VIDALERT_L
TP_CPU_FC_VCCST
TP_CPU_FC_VCCST_PWRGD
CPU_VIDSOUT CPU_PWR_DEBUG
=PP1V5R1V35_S0_CPU
=PPVCC_S0_CPU
TP_CPU_RSVD_TP
TP_CPU_RSVD_TP
TP_CPU_RSVD_TP
CPU_VCCSENSE_P
=PPVCC_S0_CPU
CPU_VIDSCLK_R
CPU_VIDSCLK
R 1 2
(^1) R
2
R 1 2
R 1 2
R0800^1
2
U
D
D
F
AM
F
AH
AN
AN
AN
AN
AR
J
J J J J
U
V
W
W
AA
AA
AA
A A A A A A AA AA AA AA
BB
B
BC
C C C C C C C C C C C C D D D D D D D D D D D D D E E E E E E E E E E E E E F F F F F F F F F F F F F G G G G G G G G G G G G G H H H H H H H H H H H H H H H H
L M
C
D
AK
AR AR AR
AT
AT AT AT AT AT
AV
AW
AW AW AW AY BB BB BB BB BB BB BB BB BD BD BD BD BE BE BE BE BE
J J J
AB
AD
AG
AJ
AJ
AK
AM
AN
AP
AP
B
E
V
U
A27A28A31A32A
AB45AB
AB AC46AC
AC8AC AD
AD AE46AE
AE8AF AG
AG AH46AH
AH AJ45AJ46AK46AK
AK
AL45AL
AL8AL AM46AM
AM8AM AN10AN12AN13AN14AN15AN16AN17AN19AN20AN21AN23AN24AN25AN26AN27AN29AN30AN32AN34AN36AN38AN39AN40AN41AN42AN43AN44AN45AN
AN8AN AP10AP12AP13AP14AP15AP16AP17AP18AP19AP20AP21AP22AP23AP24AP25AP26AP27AP29AP30AP31AP32AP33AP34AP35AP36AP37AP38AP39AP40AP41AP42AP43AP44AP46AP
AP8AP AR35AR37AR39AR41AR43AR45AR
B27B28B31B32B34B36B38B39B
H30H31H
H33H34H36H37H38H39H40H42H43H45H46H48H8H9J10J14J19J24J29J33J36J37J38J39J40J42J43J45J46J48J8J9K38K40K43K44K45K46K48K8K9L37L38L39L40L42L43L44L46L47L8M37M38M39M40M42M43M44M45M46M8M9N37N38N39N40N42N43N44N46N47N8N9P45P46P8R46R47R8R9T45T46U46U47U8U9V45V46V8W46W47W8Y45Y46Y
R0860^1
2
dvt
6.0.
8 OF 119
8 OF 94
051-
57181065
5
8121106
6 8 10 81
811086
WWW.AliSaler.Com
Apple Inc.
THEPROPRIETARY INFORMATION CONTAINED PROPERTY OF APPLE HEREIN INC. IS THE
BD
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
D
AC
PAGE TITLE
SHEET IV ALL RIGHTS RESERVED
R
D
DRAWING NUMBER SIZE
REVISION
BRANCH
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Intel recommendation: 4x 470uF 4mOhm (3 CPU-side, 1 opposite), 20x 22uF 0805 (10 CPU-side, 10 opposite near edge, 4x 10uF 0603 (2 CPU-side, 2 opposite), 20x 1uF 0402 (under CPU)
CAPS for Acoustic Control (C102E to C103F)
Apple Implementation: 9x 210uF 6mOhm, 44x 10uF 0402, 4x 10uF 0402, 20x 1uF 0402
PLACEMENT_NOTE (C1046-C1067):
CPU VCORE Decoupling
PLACEMENT_NOTE (C1000-C1019):
PLACEMENT_NOTE (C1068-C1076:
PLACEMENT_NOTE (C1024-C1045):
PLACEMENT_NOTE (C1020-C1023):
PLACEMENT_NOTE (C1090-C1097):
Apple Implementation: 2x 0.01uF 0402 (second cap is on CPU VR page)
NOTE: Intel decoupling recommendations from Shark Bay Mobile Platform Power Delivery Design Guide (doc #487822, Rev 0.8 dated January 2012), Section 5.
Intel recommendation: 2x 0.01uF 0402 (1 near CPU, 1 near SVID pull-ups)
CPU VCCIO Decoupling
(Z = 1.5mm, place on tall side next to CPU & under heat pipe)
PLACEMENT_NOTE (C1098-C1099):
PLACEMENT_NOTE (C1080-C1089):
Apple Implementation: 2x 330uF, 8x 10uF 0603, 10x 1uF 0402
Intel recommendation: 2x 330uF, 8x 10uF 0603, 10x 1uF 0402
CPU VDDQ Decoupling
CAPS for Acoustic Control (C109A to C102D)
0402
1UF
X6S-CERM10V
10%
Place on bottom side of U
10V 0402
Place on bottom side of U
10% X6S-CERM
1UF
X6S-CERM 0402
Place on bottom side of U
10%10V
1UF
0402-
4VX5R-CERM
20UF
CRITICAL
Place near inductors on bottom side. NO STUFF
20%
10%10V X6S-CERM 0402
Place on bottom side of U
1UF
0402
Place on bottom side of U
1UF
X6S-CERM10V 10V 10% 0402
Place on bottom side of U
10% X6S-CERM
1UF
0402
Place on bottom side of U
1UF
X6S-CERM10V
10% X6S-CERM 0402
Place on bottom side of U
1UF
10V10% 0402
Place on bottom side of U
10V10%
1UF
X6S-CERM 0402 X6S-CERM
Place on bottom side of U
1UF
10V10%
0402-
4VX5R-CERM
20UF
NO STUFF
CRITICAL
Place near inductors on bottom side.
20% 0402-
4VX5R-CERM
20UF
CRITICAL
Place near inductors on bottom side.
NO STUFF
20% 0402-
4VX5R-CERM
20UF
CRITICAL
Place near inductors on bottom side.
NO STUFF
20% 0402-
4VX5R-CERM
20UF
Place near inductors on bottom side.
CRITICAL
20%
NO STUFF
0402-
4V X5R-CERM
20UF
Place near U0500 on bottom side
NO STUFF
20% 0402-
4V X5R-CERM
20UF
Place near U0500 on bottom side
20%
NO STUFF
0402-
4V X5R-CERM
20UF
Place near U0500 on bottom side
20%
NO STUFF
0402-
4V X5R-CERM
20UF 20%
Place near U0500 on bottom side NO STUFF
0402-
4VX5R-CERM
20UF
Place near inductors on bottom side.
NO STUFF
20%
CRITICAL
0402-
4VX5R-CERM
20UF
NO STUFF
CRITICAL
20% 0402-
4VX5R-CERM
20UF
CRITICAL
Place near inductors on bottom side. NO^ STUFF
20% 0402-
4VX5R-CERM
20UF
CRITICAL
Place near inductors on bottom side. NO STUFF
20% 0402-
4VX5R-CERM
20UF
CRITICAL
Place near inductors on bottom side. NO STUFF
20% 0402-
4VX5R-CERM
20UF
Place near inductors on bottom side.
CRITICAL
NO STUFF
20% 0402-
4VX5R-CERM
20UF
Place near inductors on bottom side.
CRITICAL
20%
NO STUFF
4VX5R-CERM
20UF
Place near inductors on bottom side.
20%
NO STUFF
CRITICAL
0402-2 0402-
4VX5R-CERM
20UF
Place near inductors on bottom side.
20%
NO STUFF
CRITICAL
0402-
4VX5R-CERM
20UF
CRITICAL
Place near inductors on bottom side. NO STUFF
20% 0402-
4VX5R-CERM
20UF
Place near inductors on bottom side.
CRITICAL
NO STUFF
20%
0.01UF 10%
X7R-CERM
16V 0402
X6S-CERM
Place on bottom side of U
0402
1UF 10%10V 1UF
X6S-CERM 0402
Place on bottom side of U
10%10V X6S-CERM 0402
10%
Place on bottom side of U
10V
1UF 1UF
10V 0402
Place on bottom side of U
10% X6S-CERM
1UF
X6S-CERM 0402
Place on bottom side of U
10%10V X6S-CERM 0402
Place on bottom side of U
10V^ 1UF^ 10%10V
0402
Place on bottom side of U
1UF
X6S-CERM
1UF 10%
X6S-CERM 0402
Place on bottom side of U
10V10% 0402
Place on bottom side of U100.
1UF
X6S-CERM
10V10% X6S-CERM 0402
Place on bottom side of U
10%^ 1UF 10V
Place near U0500 on bottom side
10UF 20%
0603 X6S-CERM
4V20% 4V
Place near U0500 on bottom side
10UF
X6S-CERM 0603 X6S-CERM
10UF 20%
4V 0603
Place near U0500 on bottom side
20%
Place near U0500 on bottom side
10UF
0603
4V X6S-CERM
20%
Place near U0500 on bottom side
10UF
0603 X6S-CERM
20% 4V
Place near U0500 on bottom side
10UF
X6S-CERM
4V 0603 0603
20%
Place near U0500 on bottom side
10UF
X6S-CERM
4V
Place near U0500 on bottom side
10UF 20%
0603 X6S-CERM
4V
4V
20UF
Place near inductors on bottom side.
CRITICAL
20%
NO STUFF
X5R-CERM 0402-
4VX5R-CERM
20UF
Place near inductors on bottom side.
CRITICAL
20%
NO STUFF
0402-
20UF
Place near inductors on bottom side.
CRITICAL
NO STUFF
20% 0402-
X5R-CERM4V 0402-
4VX5R-CERM
20UF
Place near inductors on bottom side.
CRITICAL
NO STUFF
20%
POLY-TANT D15T-ECGLT-COMBO
2.0V
330UF-6MOHM
CRITICAL
20% D15T-ECGLT-COMBO
CRITICAL
2.0V20%
330UF-6MOHM
POLY-TANT
0402
Place on bottom side of U
10%10V X6S-CERM
1UF
0402
Place on bottom side of U
1UF
X6S-CERM10V
10% 0402
Place on bottom side of U
1UF
10V10%X6S-CERM 0402
Place on bottom side of U
10%10V X6S-CERM
1UF
X6S-CERM 0402
Place on bottom side of U
10%10V
1UF
0402
Place on bottom side of U
1UF
X6S-CERM10V
10% 0402
Place on bottom side of U
X6S-CERM
10%10V
1UF 1UF
10%10V 0402
Place on bottom side of U
X6S-CERM 0402 X6S-CERM
Place on bottom side of U
10%10V
1UF
X6S-CERM 0402
Place on bottom side of U
10%10V
1UF
0402-
20%^ 20UF
X5R-CERM
4V
CRITICAL
Place near inductors on bottom side.
0402-
20UF20%
X5R-CERM
4V
Place near inductors on bottom side.
CRITICAL
ACAPS:A
0402-
20%^ 20UF 4V
Place near inductors on bottom side.
CRITICAL
0402-2^ X5R-CERM
4V
Place near inductors on bottom side.
X5R-CERM
20%^ 20UF
CRITICAL
0402-
20% X5R-CERM
4V
Place near inductors on bottom side.
CRITICAL
20UF
0402-
20%^ 20UF
X5R-CERM
4V
Place near inductors on bottom side.
CRITICAL
ACAPS:A
0402-
20%^ 20UF
X5R-CERM
4V
Place near inductors on bottom side.
CRITICAL
ACAPS:A
0402-
20UF20%
X5R-CERM
4V
Place near inductors on bottom side.
CRITICAL
0402-
20UF20%
X5R-CERM
4V
CRITICAL
Place near inductors on bottom side. NO STUFF
0402-
20%^ 20UF
X5R-CERM
4V
CRITICAL
Place near inductors on bottom side.
ACAPS:A
0402-
20UF20%
X5R-CERM
4V
Place near inductors on bottom side.
CRITICAL
ACAPS:A
0402-
20%^ 20UF
X5R-CERM
4V
CRITICAL
Place near inductors on bottom side.
ACAPS:A
0402-
20%^ 20UF
X5R-CERM
4V
Place near inductors on bottom side.
CRITICAL
ACAPS:A
0402-
20UF20%
X5R-CERM
4V
Place near inductors on bottom side.
CRITICAL
ACAPS:A
0402-
20%^ 20UF
X5R-CERM
4V
CRITICAL
Place near inductors on bottom side. ACAPS:A
0402-
20%^ 20UF
X5R-CERM
4V
Place near inductors on bottom side.
CRITICAL
ACAPS:A
0402-
20UF20%
X5R-CERM
4V
Place near inductors on bottom side.
CRITICAL
ACAPS:A
0402-
20UF20%
X5R-CERM
4V
Place near inductors on bottom side.
CRITICAL
NO STUFF
0402-
20%^ 20UF
X5R-CERM
4V
Place near inductors on bottom side.
CRITICAL
NO STUFF
0402-
20%^ 20UF
X5R-CERM
4V
CRITICAL
NO STUFF
0402-
20UF
X5R-CERM4V
20%
CRITICAL
Place near inductors on bottom side.
ACAPS:A
0402-
20UF
X5R-CERM4V
20%
CRITICAL
Place near inductors on bottom side. NO STUFF
0402-
20UF
X5R-CERM
4V
Place near inductors on bottom side.
CRITICAL
20% 0402-
20% X5R-CERM
4V
Place near inductors on bottom side.
CRITICAL
20UF
ACAPS:A
2.5VPOLY-TANT CASE-B2S
CRITICAL
210UF 20%
CRITICAL
2.5V
210UF
POLY-TANTCASE-B2S
20% POLY-TANTCASE-B2S
210UF
CRITICAL
2.5V
20% POLY-TANT
20% 2.5V CASE-B2S
210UF
CRITICAL
POLY-TANT2.5VCASE-B2S
210UF
CRITICAL
20% POLY-TANT2.5V
210UF
CRITICAL
20% CASE-B2S CASE-B2S
20% POLY-TANT2.5V
210UF
CRITICAL
POLY-TANT
CRITICAL
210UF
2.5V
20% CASE-B2S
CRITICAL
CASE-B2SPOLY-TANT
20% 2.5V
NO STUFF
210UF
0402-
4V X5R-CERM
20UF
CRITICAL
20%
Place near inductors on bottom side.
0402-
4V X5R-CERM
20UF
CRITICAL
20%
ACAPS:A
0402-
4V X5R-CERM
20UF 20%
CRITICAL
0402-
4V X5R-CERM
20UF
NO STUFF
CRITICAL
20% 0402-
4V X5R-CERM
20UF
CRITICAL
NO STUFF
20% 0402-
4V20% X5R-CERM
20UF
CRITICAL
0402-
4V X5R-CERM
20UF
CRITICAL
20% 0402-
4V X5R-CERM
20UF
CRITICAL
20%
ACAPS:A
0402-
4VX5R-CERM
20UF
20%
ACAPS:A
CRITICAL
0402-
4VX5R-CERM
20UF
CRITICAL
20%
ACAPS:A
0402-
4VX5R-CERM
20UF
20%
CRITICAL
ACAPS:A
0402-
4VX5R-CERM
20UF
CRITICAL
20%
ACAPS:A
0402-
4V
20UF
CRITICAL
20%
ACAPS:A
X5R-CERM 0402-
4VX5R-CERM
20UF
NO STUFF
20%
CRITICAL
0402-
4V
20UF
20%
CRITICAL
ACAPS:A
X5R-CERM 0402-
4VX5R-CERM
20UF
20%
CRITICAL
NO STUFF
0402-
4VX5R-CERM
20UF
CRITICAL
20%
ACAPS:A
0402-
4VX5R-CERM
20UF
CRITICAL
20% 0402-
4VX5R-CERM
20UF
20%
CRITICAL
NO STUFF
0402-
20%
CRITICAL
20UF
X5R-CERM4V 0402-
4VX5R-CERM
20UF
20%
CRITICAL
ACAPS:A
0402-
4VX5R-CERM
20UF
20%
CRITICAL
NO STUFF
0402-
4VX5R-CERM
20UF
CRITICAL
20%
ACAPS:A
0402-
4VX5R-CERM
NO STUFF
CRITICAL
20%
20UF
CRITICAL
330UF-9MOHM
D15T-
2.5VPOLY-TANT
20%
NO STUFF
SYNC_MASTER=CLEAN_J15 SYNC_DATE=05/02/
CPU Decoupling
=PP1V5R1V35_S0_CPU
PPVCCIO_S0_CPU
=PPVCC_S0_CPU
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
32
(^1) C
32
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C
2
(^1) C103F
2
(^1) C103E
2
(^1) C103D
2
(^1) C103C
2
(^1) C103B
2
(^1) C103A
2
(^1) C102F
2
(^1) C102E
2
(^1) C101B
2
(^1) C101A
2
(^1) C109F
2
(^1) C109E
2
(^1) C109D
2
(^1) C109C
2
(^1) C109B
2
(^1) C109A
2
(^1) C102D
2
(^1) C102C
2
(^1) C102B
2
(^1) C102A
2
(^1) C101E
2
(^1) C101D
2
(^1) C101C
2
(^1) C101F
2
(^1) C
32
dvt
051-
6.0.
10 OF 119
10 OF 94
812186
5718865
8186
WWW.AliSaler.Com
IN
IN
IN
IN
IN IN OUT
IN
OUT OUT
OUT
OUT
OUT
IN
OUT
IN
IN
IN
OUT OUT
OUT OUT
IN
IN
OUT OUT
OUT
OUT
OUT
OUT
NC
NC
HDA_SDI HDA_SDI
TP TP
HDA_DOCK_RST*/GPIO
SATA_RXP
SATA_RXP5/PERP
SATA_RXN5/PERN
TP
SRTCRST*
RTCX RTCX
HDA_BCLK
DOCKEN*/GPIO
SATA_RCOMP
SATA_TXN
SATA_TXP4/PETP
SATA_TXP
SATA_TXN4/PETN
SATA_TXN
SATA0GP/GPIO
SATALED*
SPKR
JTAG_TDI JTAG_TDO
JTAG_TMS
TP
JTAG_TCK
INTRUDER*
HDA_SYNC
HDA_SDI
HDA_SDO
SATA_RXP
SATA_RXN
SATA_TXN SATA_TXP
SATA_RXN SATA_RXP SATA_TXN
TP
SATA_IREF
SATA1GP/GPIO
SATA_TXP SATA_RXN SATA_RXP
RTCRST*
INTVRMEN
SATA_RXN
SATA_RXP4/PERP
SATA_RXN4/PERN
SATA_TXP
SATA_TXP5/PETP
SATA_TXN5/PETN
HDA_SDI
HDA_RST*
JTAG
(1 OF 11)
RTC
AZALIA
SATA
CLOCKS
(2 OF 11)
PCIECLKRQ2/GPIO20/SMI
CLKOUT_33MHZ
PCIECLKRQ5*/GPIO
CLKOUT_PCIE_P
CLKOUT_PCIE_N
PCIECLKRQ0*/GPIO
CLKOUT_PEG_A_N CLKOUT_PEG_A_P
CLKOUT_PCIE_P
CLKOUT_PCIE_N
CLKOUT_PCIE_N CLKOUT_PCIE_P
TP
TP
CLKOUT_PCIE_N CLKOUT_PCIE_P
PCIECLKRQ6*/GPIO
CLKOUT_PCIE_P
CLKOUT_PCIE_N
PCIECLKRQ1*/GPIO
CLKOUT_DPNS_N CLKOUT_DPNS_P
CLKOUT_DMI_N CLKOUT_DMI_P
CLKOUT_PCIE_N CLKOUT_PCIE_P
PEG_A_CLKRQ*/GPIO
CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P
CLKOUT_DP_P
CLKOUT_DP_N
CLKOUT_PCIE_P
CLKOUT_PCIE_N
XTAL25_OUT
XTAL25_IN
ICLK_IREF
DIFFCLK_BIASREF
CLKIN_GND_N CLKIN_GND_P
CLKIN_DMI_P
CLKIN_DMI_N
CLKOUT_33MHZ
CLKIN_SATA_P
CLKIN_SATA_N
CLKOUTFLEX0/GPIO
CLKIN_33MHZLOOPBACK
CLKOUT_33MHZ CLKOUT_33MHZ
CLKOUTFLEX2/GPIO
CLKOUTFLEX1/GPIO
CLKOUTFLEX3/GPIO
CLKOUT_33MHZ
REFCLK14IN
CLKIN_DOT96_P
CLKIN_DOT96_N
PCIECLKRQ3*/GPIO
PEG_B_CLKRQ*/GPIO
PCIECLKRQ4*/GPIO
PCIECLKRQ7*/GPIO
CLKOUT_PEG_B_P
CLKOUT_PEG_B_N
CLKOUT_PCIE_N CLKOUT_PCIE_P
OUT OUT
OUT OUT
OUT
OUT
OUT
IN IN OUT OUT
OUT OUT IN
NC
NC
NC
NC
NC
NC
NC
OUT
OUT
OUT
IN
IN
IN
OUT OUT
Apple Inc.
THEPROPRIETARY INFORMATION CONTAINED PROPERTY OF APPLE HEREIN INC. IS THE
8 7 5 4 2 1
BB
D
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
D
A
C
PAGE TITLE
SHEET IV ALL RIGHTS RESERVED
R
D
DRAWING NUMBER SIZE
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.
If HDA = S0, must also ensure that signal cannot be high in S3.
(IPD)
(IPD-PLTRST#)
(IPU)
1.5V -> 1.1V
(IPD-PWROK)
(IPD-PWROK)
(IPD-PWROK)
(IPD-PWROK)
(IPU-RSMRST#)
(IPU-RSMRST#)
(IPD-PWROK) (IPD-PWROK) (IPD-PWROK) (IPD-PWROK) (IPD-PWROK)
Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.
(IPU-PLTRST#)
(IPD)
(IPD)
Unused clock terminations for FCIM Mode
(IPD-boot)
(IPD-boot)
(IPU)
(IPD)
Unused
(if not combo w/SD Card)
Reserved: Ethernet
SATA Port assignments:
PCIe:
Unused
Reserved: ODD
Primary HDD/SSD (SATA only)
Secondary HDD/SSD (SATA only)
NOTE: ENET pair only used if SD Card Reader is USB3.
(IPD)
(IPD-DOCKEN#?)
CLKOUT_PEG outputs can be used for those devices.
If 2 or less devices are attached to PEG the
while PCH-attached PCIe devices use the other set.
PEG-attached (CPU) PCIe devices must use one set,
NOTE: SSC control is ganged on PCIe 0-3 and 4-7 clocks.
8719
8851
MF 201
5% 1/20W
330K 1M
MF 201
5% 1/20W
20K
201 MF
1/20W5%
20K
MF 201
5%1/20W
1UF
X5R 402
10%10V
1UF
X5R 402
10%10V
PLACE_NEAR=U1100.AY5:2.54mm
7.5K
MF 201
1% 1/20W 8211
8318 8318
8318 8318
1/16W
1%
402
MF-LF
MF 201
1% 1/20W
1K
19 87
18 18
8833
8833
8836
18
8836
3411
3511
2811
6 86 6 86
6 86 6 86
19 88
8211
8828 8828
4.7K
5% 1/20W MF 201
5% 1/20W MF 201
4.7K
5% 1/20W MF 201
10K
5% 1/20W MF 201
10K
5% 1/20W MF 201
10K
5% 1/20W MF 201
10K
5% 1/20W MF 201
10K
5% 1/20W MF 201
10K
5% 1/20W MF 201
10K
5% 1/20W MF 201
10K
10K
5% 1/20W MF 201
10K
5% 1/20W MF 201
5% MF 201
10K
1/20W
10K
10K 5%^ 1/20W MF^201
5% 1/20W MF 201
8851
8851
8851
8851
5% 1/20W MF 201
10K 5%^ 1/20W MF^201
10K
5% 1/20W MF 201
10K 5%^ 1/20W MF^201
10K
5% 1/20W MF 201
10K 5%^ 1/20W MF^201
10K
5% 1/20W MF 201
10K
1/20W
10K
5% MF 201
5% 1/20W MF 201
10K
FCBGA
MOBILE
LYNXPOINT
OMIT_TABLE
FCBGA
OMIT_TABLE
LYNXPOINT
MOBILE
6 86 6 86
8684 8684
PLACE_NEAR=U1100.B25:1.27mm5%^ 1/20W MF^201
MF
PLACE_NEAR=U1100.A24:1.27mm5%^ 1/20W^201
PLACE_NEAR=U1100.A22:1.27mm
5% 1/20W MF 201
5% 1/20W MF 201
PLACE_NEAR=U1100.C24:1.27mm
8819
8819
8819
84 84 84 84
84 84 18
7.5K
201
PLACE_NEAR=U1100.AN44:2.54mm 1% MF
1/20W
8211
5% 1/20W MF 201
10K
8834
8834
11 82
84
84
84 84
SYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/
PCH RTC/HDA/JTAG/SATA/CLK
ENET_CLKREQ_L
TP_PCIE_CLK100M_PEGBN
PCH_PEGCLKRQB_L_GPIO
ENET_MEDIA_SENSE_RDIV
XDP_PCH_TCK
ENET_MEDIA_SENSE_RDIV
DP_TBT_SEL
HDA_SDOUT
HDA_SDIN
PCH_CLK96M_DOT_N
PCH_SPKR
DP_TBT_SEL
PCH_SRTCRST_L
PCH_INTRUDER_L
HDA_SYNC_R
=PP1V5_S0_PCH_VCCVRM_BIAS
PCH_INTRUDER_L
PCH_INTVRMEN_L
PCH_SRTCRST_L
RTC_RESET_L
=PPVRTC_G3_PCH
SYSCLK_CLK25M_SB
TP_HDA_SDIN
TP_HDA_SDIN
PCH_DIFFCLK_BIASREF
PCH_CLK14P3M_REFCLK
PCH_CLKIN_GNDN
PCH_CLKIN_GNDP
PCH_CLK100M_SATA_P
TP_PCH_GPIO66_CLKOUTFLEX
TP_PCH_GPIO67_CLKOUTFLEX
PCIE_CLK100M_PCH_N
PCIE_CLK100M_PCH_P
DMI_CLK100M_CPU_N
TP_PCIE_CLK100M_ENETN
SYSCLK_CLK32K_RTC
HDA_BIT_CLK_R
HDA_RST_R_L
HDA_BIT_CLK
XDP_PCH_TMS
XDP_PCH_TDO
=PP1V5_S0_PCH_SATA
SSD_CLKREQ_L
TP_PCH_GPIO64_CLKOUTFLEX
PCH_SATALED_L
ENETSD_CLKREQ_L
AP_CLKREQ_L
PCH_CLKRQ5_L_GPIO
PEG_CLKREQ_L
PCH_CLKRQ7_L_GPIO
ENET_CLKREQ_L
HDA_SYNC
HDA_RST_L
PCH_INTVRMEN_L
RTC_RESET_L
PCH_SPKR
XDP_PCH_TDI
TP_PCH_GPIO65_CLKOUTFLEX
PCH_CLK33M_PCIIN
SYSCLK_CLK25M_SB_R
PCH_CLKRQ5_L_GPIO44 PCH_CLK96M_DOT_P
TP_PCIE_CLK100M_PE5N
TP_PCI_CLK33M_OUT
PCH_CLKRQ7_L_GPIO
TP_PCIE_CLK100M_SWN
TP_PCIE_CLK100M_SWP
TP_PCIE_CLK100M_PE5P
TP_PCIE_CLK100M_GPUN
TP_PCI_CLK33M_OUT
TP_PCIE_CLK100M_GPUP
PCIE_CLK100M_SSD_P
PCIE_CLK100M_SSD_N
PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P
XDP_DD3_AP_CLKREQ_L
PCIE_CLK100M_CAMERA_N
PCIE_CLK100M_CAMERA_P
CAMERA_CLKREQ_L
TBT_CLKREQ_L
PEG_CLKREQ_L
PCIE_CLK100M_TBT_N
PCIE_CLK100M_TBT_P
ITPXDP_CLK100M_N
ITPXDP_CLK100M_P
LPC_CLK33M_SMC_R
LPC_CLK33M_LPCPLUS_R
PCH_CLK33M_PCIOUT
SATARDRVR_EN
DP_AUXCH_ISOL_L
=PP1V5_S0_PCH_CLK
PCH_CLK100M_SATA_N
CPU_CLK135M_DPLLREF_P
CPU_CLK135M_DPLLREF_N
CPU_CLK135M_DPLLSS_P
CPU_CLK135M_DPLLSS_N
DMI_CLK100M_CPU_P
TP_PCIE_CLK100M_PEGBP
PCH_PEGCLKRQB_L_GPIO
TP_PCIE_CLK100M_ENETP
CAMERA_CLKREQ_L
TBT_CLKREQ_L
TP_HDA_SDIN
HDA_SDOUT_R
TP_PCIE_ENET_R2D_CN
TP_PCIE_ENET_R2D_CP
TP_SATA_F_D2RN
TP_PCIE_ENET_D2RP
TP_PCIE_ENET_D2RN
TP_SATA_D_D2RN
TP_SATA_D_R2D_CP
TP_SATA_D_D2RP
TP_SATA_D_R2D_CN
TP_SATA_F_R2D_CP
TP_SATA_F_D2RP
TP_SATA_F_R2D_CN
XDP_DC0_DP_AUXCH_ISOL_L
XDP_DC1_SATARDRVR_EN
TP_SATA_ODD_R2D_CP
TP_SATA_ODD_R2D_CN
TP_SATA_ODD_D2RP
TP_SATA_ODD_D2RN
SATA_A_R2D_C_P
SATA_A_R2D_C_N
SATA_A_D2R_P
SATA_A_D2R_N
SATA_B_D2R_N
SATA_B_D2R_P
SATA_B_R2D_C_N
SATA_B_R2D_C_P
PCH_SATALED_L
PCH_SATA_RCOMP
SSD_CLKREQ_L
PCIE_CLK100M_ENETSD_N
PCIE_CLK100M_ENETSD_P
XDP_DD2_ENETSD_CLKREQ_L
=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO
R
1
2
R
1
2
R1102^1
2
(^1) R
2
(^1) C
2
C1102 1
2
R1130^1
2
R 1 2
R
1
R1177 1 2 2
R1178 1 2
R1134 1 2
R1142 1 2 R1169 1 2 R1144 1 2 R1145 1 2 R1147 1 2 R1114 2 1 R1115 1 2
R1143 1 2
R1133 1 2
R1179 1 2
R1146 1 2 R1148 1 2
R1191 1 2
R1192 1 2
R1193 1 2
R1194 1 2
R1195 1 2
R1196 1 2
R1197 1 2
R1170 1 2
R1171 1 2
U
B
BC
C
L K
G
F
AA
AG
AB
AB
AE
AD
AD
AD
D
B B
AT
AU
BD
AY
BC
BC
BB
BC
BD
BC
BE
BE
BD
BE
BB
BE
AW
AV
AY
AR
AR
AV
AP
AY
AW
AW
AT
AW
AR
AP
AL
AL
B
AB
C
F
BB
BA
U
D
AY AW
H
G
AR
AT
BE BC
D E B F A
AF AF
AJ
AJ
AF
AF
AF
AH
AH
Y
AA
AB
AD
AF
AE
AB
AJ
Y
AA
AB
AD
AF
AE
AB
AJ
AB AB
Y Y
C F F F
AN
AN
AM
AB
AF
AF
T
V
AA
AE
Y
AF
U
F
AD
AD
AM
AL
R1110 1 2
R1113 1 2
R1111 1 2
R1112 1 2
R 2 1
R1176 1 2
11 OF 94
11 OF 119
6.0.
051-
dvt
84
11 11 82
88
11 11 82
8811 8811
88
17
11 88 11 88
11 88
11
12 15 81
84
84
88
88
84 84
88 88
84
88
88
81
11 34
84
11
18 18 33
11 11 82 11
11 82
8811 11
11
84
87
11 88
84
84
11
84 84
84
82
8420
82
18
18 82
81
88
84 11
84
11 35 11 28
84
8819
84
84
84
84 84
84
84 84
84
84
84
84
11
87
12 13 14 81 12 14 20 29 81
BI
BI
BI BI
IN IN
OUT
IN
OUT
IN
BI
IN
OC1/GPIO OC2/GPIO
OC5*/GPIO
OC0*/GPIO
OC3*/GPIO
OC6*/GPIO
OC4*/GPIO
OC7*/GPIO
USB2P
USB2N
USB2P
USB2N
USB2N
USB2N
USB2P
USB2P
USB2P
USB2P
USB2P
USB2P
PETN
PETP
PETN
PETN
PETN1_USB3TN
PCIE_IREF
USB3TP
USB3TN
USB3TN
PETN PETP
PETN
PCIE_RCOMP
USB3TN
USB3TN
USB3TP
PETP
PETN
PETP1_USB3TP
TP
USB3TP
USB3TP
PETP
TP
USB2N
USB2N
USB2N
PERN
PERP
PERP1_USB3RP
PERP
PERN
PERN
PERN1_USB3RN
USB3RN
USB3RN
PERP
USB3RP
PERN7 USB3RP PERP
PERN
PERN2_USB3RN
PERP
PERP2_USB3RP
USB3RN
USB3RN
USB3RP
USB3RP
PERP
PERN
USB2N
USB2N
USB2N
USB2N USB2P
USB2N
USB2P
USB2N
USB2P
USB2P
PETP
USB2P
PETP2_USB3TP
PETN2_USB3TN
PETP
USB2N USB2P
TP
TP
USBRBIAS* USBRBIAS
(9 OF 11)
PCI-EUSB
BI
IN IN OUT OUT
IN
IN
OUT OUT
IN
IN
OUT OUT
IN
IN
OUT OUT
OUT
OUT
SML0CLK
SML1ALERT/PCHHOT/GPIO
LDRQ1*/GPIO
LAD
TP
TP
TP
TP
SPI_CS1*
SERIRQ
SPI_CS0*
SPI_IO SPI_IO
SPI_CLK
SPI_CS2*
SPI_MISO
SPI_MOSI
LAD
SML1DATA/GPIO
CL_RST*
SML1CLK/GPIO
LDRQ0*
TD_IREF
CL_CLK CL_DATA
SMBALERT*/GPIO
SMBCLK SMBDATA
SML0ALERT*/GPIO
LAD
SML0DATA
LFRAME*
LAD
LPCSMBUS
(3 OF 11)
SPI
C-LINK
IN BI
BI
OUT
BI
OUT
OUT BI
BI
OUT
BI BI BI
BI BI BI BI BI BI
NC
NC
NC
NC
NC
NC
NC
NC
BI BI
BI BI
OUT
BI
IN
IN
OUT
OUT
BI
IN
OUT
IN
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN IN
OUT OUT
IN IN OUT OUT
IN IN OUT OUT
Apple Inc.
THEPROPRIETARY INFORMATION CONTAINED PROPERTY OF APPLE HEREIN INC. IS THE
8 7 5 4 2 1
B
D
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
D
A
C
PAGE TITLE
SHEET IV ALL RIGHTS RESERVED
R
D
DRAWING NUMBER SIZE
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Unused
PCIe Port Assignments:
(& Ethernet if combo)
SD Card Reader
PCIe/USB3 Port Assignments:
USB3 Port Assignments:
SSD (Gumstick)
(PCIe-only)
Or PCIe switch if TBT/SSD
Lane 1
Lane 0
(PCIe-only)
SSD (Gumstick)
Or PCIe switch if TBT/SSD
Or PCIe switch if TBT/SSD
Or PCIe switch if TBT/SSD
SSD (Gumstick)
SSD (Gumstick)
(PCIe-only)
Lane 2
(PCIe-only)
Lane 3
Camera
AirPort
(IPU/IPD) (IPU/IPD)
(IPU)
(IPU)
(IPU-LDRQ1#?)
(IPU)
(IPU)
(IPU)
(IPU) (IPU)
(IPU) (IPD)
(IPU)
(IPU)
(IPU)
Reserved: SD (HS)
Reserved: WiFi (HS)
Ext A (LS/FS/HS)
Ext C (LS/FS/HS)
USB Port Assignments:
Reserved: PSOC (Legacy Trackpad)
Unused
Unused
Unused
Ext D (LS/FS/HS)
Reserved: Camera
Ext A (SS)
Ext B (SS)
USB3 Port Assignments:
Ext D (SS)
IR
BT
Trackpad
(IPD)
Ext C (SS)
Ext B (LS/FS/HS)
84
84
84 84
10K
5% 1/20W MF 201
5% 1/20W MF 201
10K
5% 1/20W MF 201
10K
5% 1/20W MF 201
10K
5% 1/20W MF 201
10K
5% 1/20W MF 201
10K
13 18 13 18
18
13 18
18
13 18
37 87
13 18
FCBGA
LYNXPOINT
MOBILE
OMIT_TABLE
37 87
37 87 37 87 37 87 37 87
78 83 87
78 83 87
78 87 78 87
84
84
84 84
84
84
84 84
8849
8849
FCBGA
OMIT_TABLE
LYNXPOINT
MOBILE
43 88 43 88
43 88
43 88
43 83 88
43 83 88
7.5K
1% MF 201
1/20W
PLACE_NEAR=U1100.BD29:12.7mm
33 5%^ 1/20W MF^201
5% 1/20W MF 201
1/20W MF
5% 201
5% 1/20W
MF 201
5% 1/20W MF 201
2013
83494013
10K
5% 1/20W MF 201
8883794940
8883794940
8883794940 8883794940 8883794940
1% 201
1/20W MF
8.2K
33 87 33 87 84 84 38 87 38 87
10K
5% 1/20W MF 201
10K
5% 1/20W MF 201
10K
5% 1/20W MF 201
10K
10K 5%^ 1/20W MF^201
5% 1/20W MF 201
8849 8849
4913 4913
18
5% 1/20W MF 201
10K
1K
5% 1/20W MF 201
1K
5% 1/20W MF 201
78 83 87
20
20
20
20
78 83 87
8834
8834
8834
8834
8834
8834
8834
8834
8834
8834
8834
8834
8834 8834
8834 8834
8833 8833 8833 8833
8836 8836 8836 8836
PLACE_NEAR=U1100.K24:11.4mm
MF 201
1/20W
1%
SYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/
PCH PCI-E/USB
USB3RPCIE_SD_R2D_C_P
USB3RPCIE_SD_R2D_C_N
USB3RPCIE_SD_D2R_P
USB3RPCIE_SD_D2R_N
TP_USB3_SPARE_R2D_CN
TP_USB3_SPARE_R2D_CP
TP_USB3_SPARE_D2RN
TP_USB3_SPARE_D2RP
PCIE_CAMERA_D2R_N
PCIE_CAMERA_R2D_C_P
PCIE_CAMERA_D2R_P
PCIE_CAMERA_R2D_C_N
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_SSD_R2D_C_P<0>
PCIE_SSD_D2R_N<1>
PCIE_SSD_D2R_P<1>
PCIE_SSD_R2D_C_P<1>
PCIE_SSD_R2D_C_N<1>
PCIE_SSD_D2R_P<0>
PCIE_SSD_R2D_C_N<0>
PCIE_SSD_D2R_N<0>
PCIE_SSD_D2R_N<2>
PCIE_SSD_R2D_C_N<2>
PCIE_SSD_D2R_P<2>
PCIE_SSD_R2D_C_N<3>
PCIE_SSD_R2D_C_P<3>
PCIE_SSD_D2R_P<3>
PCIE_SSD_D2R_N<3>
PCIE_SSD_R2D_C_P<2>
PCH_USB_RBIAS
LPC_AD_R<0>
SMBUS_PCH_DATA
SML_PCH_0_CLK
SML_PCH_0_DATA
SML_PCH_1_CLK
SML_PCH_1_DATA
PCH_SML0ALERT_L
SMBUS_PCH_CLK
PCH_SMBALERT_L
TP_CLINK_DATA
TP_CLINK_CLK
PCH_TD_IREF
TP_CLINK_RESET_L
SPI_MOSI_R
SPI_MISO
TP_SPI_CS2_L
SPI_CLK_R
SPI_IO<3>
SPI_IO<2>
SPI_CS0_R_L
LPC_SERIRQ
TP_SPI_CS1_L
TBT_PWR_EN_PCH
PCH_SML1ALERT_L
LPC_AD<0>
LPC_AD<2>
LPC_AD<3>
LPC_AD<1>
LPC_FRAME_L
USB_EXTA_N
USB_EXTA_P
USB_EXTC_N
USB_EXTC_P
USB_EXTB_N
USB_EXTB_P
USB_EXTD_N
USB_EXTD_P
USB_BT_N
USB_IR_N
USB_BT_P
USB_TPAD_N
USB_IR_P
USB_TPAD_P
USB3_EXTA_D2R_P
USB3_EXTA_D2R_N
USB3_EXTA_R2D_C_N
USB3_EXTB_D2R_N
USB3_EXTA_R2D_C_P
USB3_EXTB_D2R_P
USB3_EXTB_R2D_C_N
USB3_EXTC_D2R_P
USB3_EXTC_R2D_C_P
USB3_EXTD_R2D_C_N
XDP_DA0_USB_EXTA_OC_L
XDP_DA1_USB_EXTC_OC_L
XDP_DA3_CAMERA_PWR_EN
XDP_DB0_USB_EXTB_OC_L
XDP_DB1_USB_EXTD_OC_L
XDP_DB3_SDCONN_STATE_CHANGE_L
TP_USB_7P
TP_USB_WLANN
TP_USB_SDN
TP_USB_CAMERAN
TP_USB_4N
TP_USB_WLANP
TP_USB_SDP
TP_USB_4P
TP_USB_PSOCN
TP_USB_7N
TP_USB_PSOCP
TP_USB_6N
=PP1V5_S0_PCH_RCOMP
USB3_EXTD_D2R_N
USB3_EXTD_D2R_P
USB3_EXTD_R2D_C_P
XDP_DB2_SD_PWR_EN
PCH_PCIE_RCOMP
TP_LPC_DREQ0_L
LPC_FRAME_R_L
LPC_AD_R<3>
LPC_AD_R<2>
LPC_AD_R<1>
USB3_EXTC_R2D_C_N
TP_USB_CAMERAP
TP_USB_6P
XDP_DA2_SSD_PWR_EN
USB3_EXTB_R2D_C_P
USB3_EXTC_D2R_N
PCH_SML1ALERT_L
PCH_SML0ALERT_L
SPI_IO<2>
SPI_IO<3>
PCH_SMBALERT_L
XDP_DB1_USB_EXTD_OC_L
SD_PWR_EN
XDP_DB0_USB_EXTB_OC_L
SSD_PWR_EN
LPC_SERIRQ
TBT_PWR_EN_PCH
XDP_DA0_USB_EXTA_OC_L
XDP_DA1_USB_EXTC_OC_L
=PP3V3_SUS_PCH_GPIO
=PP3V3_SUS_PCH_VCC_SPI
=PP3V3_S0_PCH
CAMERA_PWR_EN
XDP_DB3_SDCONN_STATE_CHANGE_L
=PP3V3_S3RS0_CAMPWREN
=PP3V3_S3RS4_PCH_GPIO
(^1) R
2
R1367 2 1
R1368 1 2
R1361 1 2 R1362 1 2
R1360 1 2
R1369 1 2
U
P V U P M T N M
BE
BD
AW
AT
AT
AW
AT
AW
AY
AT
AN
AY
AR
AY
AR
AV
AW
AT
AN
BE
BD
BE
BE
BD
BC
BE
BD
BC
BB
BC
BC
BB
BE
BC
BD
BC
L
M
BB
B
A
B
AG
F
A
A
B
F
K
G
A
A
D
C
D
C
F
G
C
C
D
G
L
H
C
C
AR
AW
AW
AR
AP
AV
AV
AP
BE
BD
BE
BD
BD
BC
BC
BE
K
K
U
AF AF AF
A C A C
D G
B
AL
N
R U
N
U R
H
K N AJ AJ AL
AJ
AJ AJ
AH
AH
AY
BA BC
BE
BE
(^1) R
2
R1340 1 2 R1341 1 2
R1343 1 2
R1342 1 2
R1344 1 2
R1350 1 2
(^1) R
2 R1355 1 2
R1354 1 2
R1353 1 2
R1320 1 2 R1321 1 2
R1351 1 2
R1393 1 2
R1392 1 2
dvt
051-
6.0.
13 OF 119
13 OF 94
84 84
84 84
87
13
13
84
84
84
13
84
84
84
84
84
84
84 84
84
84 84
8112
84
84
13
13
13 49 13 49 13
13 18 18 78 83
13 18
18 64
13 40 49 83 13 20 13 18 13 18
11 12 14 81 15 17 81
81
18 35
13 18
81
81
OUT
OUT
BI
IN
OUT
OUT IN
BI
IN IN
OUT
IN
OUT
GPIO
GPIO
GPIO
TACH4/GPIO
SCLOCK/GPIO
THRMTRIP*
BMBUSY*/GPIO
SLOAD/GPIO
GPIO35/NMI*
GPIO
SDATAOUT1/GPIO
SDATAOUT0/GPIO
SATA5GP/GPIO
SATA3GP/GPIO
GPIO
GPIO SATA4GP/GPIO TACH0/GPIO
VSS
GPIO
PLTRST_PROC*
TP
LAN_PHY_PWR_CTRL/GPIO
TACH3/GPIO
TACH2/GPIO
TACH1/GPIO
VSS
TACH7/GPIO
TACH6/GPIO
TACH5/GPIO
PECI
PROCPWRGD
RCIN*
VSS
SATA2GP/GPIO
CPU/MISC
(6 OF 11)
GPIO
OUT
OUT
BI
OUT
IN
OUT
BI
OUT
OUT
OUT
IN
IN
IN IN
Apple Inc.
THEPROPRIETARY INFORMATION CONTAINED PROPERTY OF APPLE HEREIN INC. IS THE
B
BB
D
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
D
A
C
PAGE TITLE
SHEET IV ALL RIGHTS RESERVED
R
D
DRAWING NUMBER SIZE
REVISION
BRANCH
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
BOM GROUP BOM OPTIONS
TABLE_BOMGROUP_HEAD TABLE_BOMGROUP_ITEM
NOTE: GPIO0 pull-up/down on project-specific page
NOTE: GPIO70 pull-up/down on project-specific page
Pull-up/down on chipset support page (depends on TBT controller)
Systems with chip-down memory should add pull-downs on another page and set straps per software.
Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.
Cactus Ridge: TBT_CIO_PLUG_EVENT, requires pull-down & isolation.
(IPU-Boot/SATA5GP?)
(IPU-Boot?) (IPU-Boot?)
(IPU-Boot/SATA4GP?)
(IPU-DeepSx)
(IPU-RSMRST#)
(IPD)
Redwood Ridge: TBT_CIO_PLUG_EVENT_L, requires pull-up (S0), no isolation necessary.
(IPD-PLTRST#) (IPD-PLTRST#)
6 18 86
21
834914
8214
2014
18 2014
834914
6 41 86
RAMCFG3:H
10K
MF
1/20W 201
5%
10K
RAMCFG2:H
MF
1/20W 201
5%
RAMCFG1:H
10K
MF
1/20W 201
5%
RAMCFG0:H
10K
MF
1/20W 201
5%
4014
2014
4014
8214
FCBGA
LYNXPOINT
MOBILE
OMIT_TABLE
20K
5% 1/20W MF 201
100K
5% 1/20W MF 201
10K
5% 1/20W MF 201
10K
5% 1/20W MF 201
100K
5% 1/20W MF 201
10K
5% 1/20W MF 201
10K
5% 1/20W MF 201
100K
5% 1/20W MF 201
10K
5% 1/20W MF 201
10K
5% 1/20W MF 201
10K
5% 1/20W MF 201
29
18
10K
5% 1/20W MF 201
10K
10K 5% 1/20W^ MF^201
5% 1/20W MF 201
NO STUFF
MF5% 1/20W 201
MF 1/20W 0201
5%
MF5% 1/20W 201
6 41 86
8214
20
18
8214
6
10K
10K 5% 1/20W^ MF^201
5% 1/20W MF 201
10K
5% 1/20W MF 201
8214
10K
5% 1/20W MF 201
18
827914
1814
1K
1/16W MF-LF 402
NO STUFF
5%
18 20
SYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/
PCH GPIO/MISC/NCTF
RAMCFG_SLOT RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H
JTAG_ISP_TDO
=PP3V3_SUS_PCH_GPIO
XDP_DD0_SSD_PCIE_SEL_L
MEM_VDD_SEL_1V5_L
LPCPLUS_GPIO
JTAG_TBT_TMS_PCH
ODD_PWR_EN_L
JTAG_ISP_TCK
JTAG_ISP_TDI
PCH_RCIN_L
=PP3V3_S5_PCH_GPIO
=PP3V3_S0_PCH_GPIO
SPIROM_USE_MLB
XDP_DD1_MLB_RAMCFG
SD_SEL_PCIE_L_USB_H
JTAG_ISP_TDO
JTAG_ISP_TDI
SPIROM_USE_MLB
FW_PWR_EN_PCH
XDP_DC3_JTAG_ISP_TCK
XDP_DC2_ODD_PWR_EN_L
XDP_FC1_GPU_GOOD
XDP_DD0_SSD_PCIE_SEL_L
LPCPLUS_GPIO
MEM_VDD_SEL_1V5_L
XDP_FC0_HDD_PWR_EN
SMC_RUNTIME_SCI_L
DPMUX_UC_IRQ
FW_PME_L
PCH_RCIN_L
PCH_PROCPWRGD
PCH_PECI
PCH_A20GATE
CPU_RESET_L
PM_THRMTRIP_L
CPU_PWRGD
PM_THRMTRIP_L_R
CPU_PECI
MLB_RAMCFG
MLB_RAMCFG
=PP3V3_S0_PCH_GPIO
=PP1V05_S0_PCH_V_PROC_IO
PCH_A20GATE
FW_PME_L
SMC_RUNTIME_SCI_L
DPMUX_UC_IRQ
WOL_EN
TBT_GO2SX_BIDIR
SMC_WAKE_SCI_L
FW_PWR_EN_PCH
WOL_EN
=TBT_CIO_PLUG_EVENT_ISOL
ISOLATE_CPU_MEM_L
MLB_RAMCFG
JTAG_TBT_TMS_PCH
TBT_GO2SX_BIDIR
SMC_WAKE_SCI_L
TBT_POC_RESET_L
(^1) R
2
R1473^1
2
(^1) R
2
R1475^1
2
AT8 U
AB
Y R
AD AN AP
U
Y K
AY
AU
AV
AT
AT AK
AN
AK
BB
AM AN
AT
C
F A
G
C D G
H
AV
AN
BE BE C A
A A A A B B B B BA BC
BD
BD BD BD BE BE D E E A
N
R1411 2 1
R1495 2 1
R1491 1 2
R1492 1 2
R1493 1 2
R1494 1 2
R1484 1 2
R1490 1 2
R1496 1 2
R1485 1 2
R1412 2 1
R1498 2 1
R1450 1 2 R1455 1 2
R1470 1 2
R1440 1 2
R1456 1 2
R1486 1 2 R1499 1 2
R1413 2 1
R1489 1 2
(^1) R
2
14 OF 94
14 OF 119
6.0.
051-
dvt
14 20
11 12 13 81
14 18
14 82
14 49 83 14 20
18 18 20
14 20
14 88
12 81
11 12 14 20 29 81
14 49 83
14 88
14
8841
20
20
812920141211
15 17 81
14
14 82
14 40
14 79 82
14 82
14 82 14 40
14 82
20
WWW.AliSaler.Com
VSS
VSS VSS (10 OF 11) VSS VSS (11 OF 11) VSS Apple Inc. THEPROPRIETARY INFORMATION CONTAINED PROPERTY OF APPLE HEREIN INC. IS THE 8 7 5 4 2 1 B D C
BA
NOTICE OF PROPRIETARY PROPERTY:
PAGE D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D DRAWING NUMBER SIZE REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT FCBGA
LYNXPOINT
OMIT_TABLE MOBILE
FCBGA
OMIT_TABLE
MOBILE LYNXPOINT AL AP AV
AV
AW AY
N
AB
H
dvt
- SYM 7 OF - SYM 8 OF VSS VSS - SYM 9 OF VSS VSS - SYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/ PLACE_NEAR=U0500.D50:50.8mm
- A11 U CPU_VCCSENSE_N
- A
- A
- A
- A
- A
- A
- A
- A
- A
- AA
- AA
- AA
- AA
- AA
- AB
- AB
- AB
- AB
- AC
- AC
- AD
- AD
- AD
- AE
- AE
- AG
- AG
- AG
- AG
- AG
- AH
- AH
- AH - AJ - AJ - AJ - AK - AK - AK - AK - AK - AL - AL - AL - AL - AL - AM - AM - AM - AM - AM - AM - AN - AN - AN - AN - AN - AN - AN - AN - AP - AP - AP - AR - AR - AR - AR - AR - AR - AR - AR - AR - AR - AR - AR - AR - AT - AT - AT - AT - AT - AT - AT - AT - AT - AT - AT - AT - AT - AT - AT - AT - AT40 U - AT - AT - AT - AT - AT - AT - AT - AT - AT - AT - AT - AT - AT - AT - AT - AU - AU - AU - AU - AU - AU - AU - AU - AU - AU - AV - AV - AV - AV - AV - AV - AV - AV - AV - AV - AV - AV - AV - AV - AW - AW - AW - AW - AW - AW - AW - AW - AW - AW - AW - AW - AW - AW - AY - AY - AY - AY - AY - AY - AY - AY - AY - B - B - B - B - B - B - B - B - B - B - B - B - BA - BA - BA - BA - BA - BA - BA - BA - BA - BA - BA - BA - BA - BA - BA - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - U - AR22 AB
- BC10BC12BC15BC18BC22BC - BC - BC30BC33BC36BC38BC41BC43BC46BC - BC - BC50BC - BC - BD10BD15BD18BD36BD41BD - BD - BD51BE10BE15BE36BE41BE46BF10BF12BF15BF18BF22BF26BF30BF33BF36BF38BF41BF43BF46BF - BF7C11C15C19C22C26C30C33C37C4C40C44C49C52C8D11D15D19D22D26D30D33D37D40D44D49D8E11E15E16E17E19E20E21E22E24E25E26E30E33E37E40E44E49E51E53E8F2F26F3F30F33F37F4F40F44F49F5G11G13G
- G20G23G25G26G30G33G37G40G44G49G52G54G7G8G9H44H49H7J44J49J51J54J7K1K2K3K4K5K6K7L48L7L9M48M50M52M54M7N48N7P1P2P3P4P48P5P50P52P54P6P7R48R7T48U1U2U3U4U48U5U50U52U54U6U7V48V7V9W48W50W52W54W7Y48Y7Y9 P9G18 A49A50A8B4BA1BA54BB1BB54BD2BD53BF49BF5BF50BF6C53D2E54F54G1 D50^1 R - 9 OF - 9 OF - 6.0. - 051- - SYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/ PCH Grounds
- AL34 U
- AL
- AN
- AN
- AN
- AP
- AP
- AP
- AP
- AK
- AT
- AT
- AT
- AT
- AT
- AT
- AT
- AT
- AV
- AM
- AV
- AV
- AV
- AV
- BB
- AV
- AY
- AM
- AY
- AY
- AY
- AY
- AM - M - M - N - N - N - N - P - P - P - P
- AM - P - P - R - R - R - R - R - R - R - R
- AM - T - U - U - U - U - U - U - U - V - V
- AM - V - V - W - W - Y - Y - Y - Y - Y - Y
- AM - Y - Y - U
- AC
- AD
- AD
- AD
- AD
- AD
- AD
- AE
- AE
- AF
- AG
- AG
- AG
- AG
- AJ
- AJ
- AJ
- AJ
- AJ
- AJ
- AJ
- AK
- AK
- AK
- AK
- AL
- BC
- BB - B - B - B - B - B - B - B - BA - BD - BD - BD - AY - AT - BD - BD - BD - BD - D - AV - F - F - F - F - BC - D - G - G - G - G - H - H - H - H - H - H - H - H - H - H - K - K - K - K - K - BC
- AA
- AA
- AA
- AA
- AB
- AB
- AB - 16 OF - 16 OF - 6.0. - 051-
Apple Inc.
THEPROPRIETARY INFORMATION CONTAINED PROPERTY OF APPLE HEREIN INC. IS THE
8 7 5 4 2 1
B
D
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
D
A
C
PAGE TITLE
SHEET IV ALL RIGHTS RESERVED
R
D
DRAWING NUMBER SIZE
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
(PCH 3.3V SUSPEND RTC PWR)
(PCH 3.3V SUSPEND USB PWR)
(PCH 3.3V FUSE PWR)
670mA Max, 34mA Idle
(PCH 3.3V/1.5V HDA PWR)
(PCH 3.3V DSW PWR)
PCH VCCIO BYPASS
PCH VCCDSW3_3 BYPASS
PCH VCCSUSHDA BYPASS
(PCH 1.5V VCCVRM PWR)
PCH VCC3_3 BYPASS
(PCH 3.3V USB2 PWR)
PCH VCC3_3 BYPASS
PCH VCC3_3 BYPASS
(PCH 3.3V CLK PWR)
PCH VCCCLK3_3 BYPASS
PCH VCC3_3 BYPASS
(PCH 3.3V HVCMOS PWR)
(PCH 3.3V GPIO/LPC PWR)
PCH VCCIO BYPASS
(PCH 1.05V FDI PWR)
PCH VCCUSBPLL BYPASS
(PCH 1.05V CORE PWR)
PCH VCC BYPASS Not^ documented in^ EDS!
(PCH 1.05V USB2 PLL PWR)
(PCH 1.05V SSC PWR)
PCH VCCCLK BYPASS
PCH VCCCLK BYPASS
(PCH 1.05V SSC100 PWR)
PCH VCCCLK BYPASS
(PCH 1.05V DIFFCLK PWR)
PCH VCCCLK BYPASS
(PCH 1.05V CLK PLL PWR)
PCH CLK VCC BYPASS
(PCH 1.05V DIFFCLK135 PWR)
(PCH 3.3V THERMAL PWR)
PCH VCCSPI BYPASS
(PCH 3.3V SUSPEND PWR)
PCH VCCSUS3_3 BYPASS
(PCH 3.3V SPI PWR)
PCH VCCSUS3_3 BYPASS
PCH VCCSUS3_3 BYPASS
PCH VCCVRM BYPASS
PCH VCCIO BYPASS
(PCH 1.05V PCIe/DMI/SATA/USB3 PWR)
PCH VCCASW BYPASS
(PCH 1.05V ME CORE PWR)
??mA Max, ??mA Idle
183mA Max, 68mA Idle
Current data from LPT EDS (doc #486708, Rev 1.0).
PCH VCC BYPASS
(PCH 1.05V USB2 PWR)
PCH V_PROC_IO BYPASS
(PCH 1.05V CPU I/F PWR)
BYPASS=U1100.AG30:6.35mm
6.3VCERM 402
1UF
10%
BYPASS=U1100.AD35:6.35mm
1UF
CERM 402
6.3V10%
BYPASS=U1100.AD34:6.35mm
1UF
CERM 402
6.3V10%
BYPASS=U1100.AA30:6.35mm
1UF
CERM 402
6.3V10%
BYPASS=U1100.AM18:6.35mm
1UF
CERM 402
10%6.3V
1UF
CERM 402
10%6.3V
PLACE_NEAR=U1100.V20:2.54mm
1UF
CERM 402
10%6.3V
PLACE_NEAR=U1100.V20:2.54mm
6.3V
22UF 20%
X5R-CERM-1 603
PLACE_NEAR=U1100.V20:2.54mm
BYPASS=U1100.AE18:6.35mm
1UF
CERM 402
10%6.3V
BYPASS=U1100.AK20:6.35mm
1UF
CERM 402
10%6.3V
BYPASS=U1100.AD20:6.35mm
1UF
CERM 402
10%6.3V
BYPASS=U1100.AG18:12.7mm
10UF
X5R 603
6.3V20%
BYPASS=U1100.AA24:6.35mm
CERM 402
1UF 10%
6.3V
BYPASS=U1100.AK22:6.35mm
1UF
CERM 402
10%6.3V
BYPASS=U1100.AK18:6.35mm
6.3V10% 402 CERM
1UF
BYPASS=U1100.AK18:12.7mm
6.3V20% 603 X5R
10UF
BYPASS=U1100.AE30:6.35mm
6.3VCERM 402
1UF
10%
BYPASS=U1100.U35:6.35mm
6.3V CERM 402
1UF10%
BYPASS=U1100.AN34:6.35mm
1UF
CERM 402 6.3V10%
BYPASS=U1100.U30:6.35mm
0.1UF
20%10V 402
CERM
0.1UF
CERM
20% 402
10V
BYPASS=U1100.AJ12:6.35mm
BYPASS=U1100.AJ12:12.7mm
6.3V 402
1UF 10%
CERM
BYPASS=U1100.AJ12:6.35mm
0.1UF 20%
402 CERM
10V
BYPASS=U1100.U32:6.35mm
CERM 402
6.3V
1UF 10%
0.1UF 20%
CERM 402
10V
BYPASS=U1100.R30:6.35mm
BYPASS=U1100.AE14:6.35mm
0.01UF
0402
X7R-CERM
10% 16V
0.1UF
20% CERM10V 402 BYPASS=U1100.L24:6.35mm
0.1UF 20%
10V 402
CERM BYPASS=U1100.AK30:6.35mm
CERM 402
1UF 10%
6.3V
BYPASS=U1100.P18:6.35mm
BYPASS=U1100.AP45:6.35mm
1UF
X5R 402
10%10V
NO STUFF
BYPASS=U1100.AP45:12.7mm
10UF
X5R 603
6.3V20%
OMIT_TABLE
CRITICAL
4.7UH-170MA-0.321OHM
0603 MF-LF 402
1/16W5%
BYPASS=U1100.AF34:12.7mm^1
10UF
X5R 603
6.3V20%
BYPASS=U1100.M29:6.35mm
CERM
6.3V
1UF 10%
CERM 402 402
6.3V
1UF 10%
BYPASS=U1100.L26:6.35mmBYPASS=U1100.L29:6.35mm
CERM 402
6.3V
1UF 10%
10V20% CERM
0.1UF
402 BYPASS=U1100.A16:6.35mm
0.1UF 20%
BYPASS=U1100.R20:6.35mm
402
CERM10V
1UF
CERM 402
6.3V10%
BYPASS=U1100.AD12:6.35mm
BYPASS=U1100.K8:6.35mm
6.3V^ 1UF10%
CERM 402
0.1UF
20%10V 402
CERM BYPASS=U1100.R26:6.35mm
0.1UF20% 10V
CERM 402 BYPASS=U1100.A26:6.35mm
SYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/
PCH DECOUPLING
113S0022 1 RES,FF,0 OHM,(020OHM MAX),2A,0603 L
=PP3V3_SUS_PCH_VCCSUS_USB
=PP1V05_S0_PCH_V_PROC_IO
=PP3V3_S0_PCH_VCCCLK3_
=PP1V05_S0_PCH_VCC_CLK
=PP1V05_S0_PCH_VCCIO_FDI
=PP3V3R1V5_S0_PCH_VCCSUSHDA
=PP3V3_S5_PCH_VCCDSW
=PP3V3_S0_PCH_VCC_FUSE
=PP3V3_S0_PCH_VCC3_3_THRM
=PP3V3_S0_PCH_VCC3_3_HVCMOS
=PP1V05_S0_PCH_VCCUSBPLL
=PP1V05_S0_PCH_VCCIO
=PP1V05_S0_PCH_VCC
=PP1V05_S0_PCH_VCCCLK_SSC
=PP1V05_S0_PCH_VCCCLK_SSC
=PP1V05_S0_PCH_VCCCLK_CLK
=PP1V05_S0_PCH_VCCCLK_CLK
=PP3V3_S0_PCH_VCC3_3_USB
=PP3V3_SUS_PCH_VCCSUS_GPIO =PP3V3_S0_PCH_VCC3_3_GPIO
=PP3V3_SUS_PCH_VCC_SPI
=PP3V3_SUS_PCH_VCCSUS_RTC
=PP1V05_S0M_PCH_VCCASW
PP1V05_S0_PCH_VCC_CLK_R
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.2 MM
=PP1V5_S0_PCH_VCCVRM_USB
=PP1V5_S0_PCH_VCCVRM_PCIE
=PP1V5_S0_PCH_VCCVRM_SATA
=PP1V5_S0_PCH_VCCVRM_CLK
=PP1V5_S0_PCH_VCCVRM_THRM
=PP1V5_S0_PCH_VCCVRM_FDI
=PP1V5_S0_PCH_VCCVRM
=PP1V5_S0_PCH_VCCVRM_BIAS
=PP1V05_S0_PCH_VCCIO_USB
MIN_NECK_WIDTH=0.075 MM
PP1V05_S0_PCH_VCC_CLK_F
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.2 MM
C1777 1
2
C1778 1
2
C1780 1
2
C1782 1
2
(^1) C
2
(^1) C
2
(^1) C
2
C1750 1
2
(^1) C
2
(^1) C
2
(^1) C
2
C1755 1
2
(^1) C
2
(^1) C
2
(^1) C
2
C1760 1
2
C1776 1
2
C1770 1
2
C1772 1
2
C1774 1
2
(^1) C
2
C1785 1
2
(^1) C
2
C1723 1
2
C1726 1
2
C1728 1
2
C1730 1
2
C1732 1
2
C1734 1
2
(^1) C
2
C1790 1
2
L
1 2
R 1 2
C1740 1
2
C1722 1
2
C1721 1
2
C1720 1
2
C1700 1
2
C1704 1
2
C1702 1
2
C1708 1
2
C1706 1
2
C1710 1
2
17 OF 94
17 OF 119
6.0.
051-
dvt
8115
811514
8115
81
8115
811915
8115
8115
8115
8115
8115
8115
8115
8115
8115
8115
8115
8115
8115 8115
811513
8115
8115
15 15 15 15 15
15
81
11
8115
15
IN
IN
OUT
OUT
IN
IN OUT
OUT
OUT
OUT
OUT
NC
NC
IN
OUT
OUT
D S
G
S
D
G
OUT OUT
IN OUT
IN
Y
A
B 08
Y
A
B 08
IN
32.768K
GND THRM
VOUT
X X
25M_A 25M_B 25M_C
VIOE_25M_A VIOE_25M_B VIOE_25M_C
VG3HOT
NC VDD
PAD
Apple Inc.
THEPROPRIETARY INFORMATION CONTAINED PROPERTY OF APPLE HEREIN INC. IS THE
8 7 5 4 2 1
BD
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
D
A
C
PAGE TITLE
SHEET IV ALL RIGHTS RESERVED
R
D
DRAWING NUMBER SIZE
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PCH PWROK Generation
System RTC Power Source & 32kHz / 25MHz Clock Generator
NOTE: ALL_SYS_PWRGD must remain low until at
PCH Reset Button
WF: Do we need this?
least 5ms after all rails are valid.
PCH 33MHz Clocks
IPD = 9-50k
PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
PCH ME Disable Strap
Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.
If high, ME is disabled. This allows for full re-flashing of SPI ROM.
SMC controls strap enable to allow in-field control of strap setting.
For SB RTC Power
+V3.3A should be first
create VDD_RTC_OUT.
internally ORed to
VBAT and +V3.3A are
to reduce VBAT draw.
available ~3.3V power
Coin-Cell & G3Hot: 3.42V G3Hot
Coin-Cell: VBAT (300-ohm & 10uF RC)
No Coin-Cell: 3.42V G3Hot (no RC)
No bypass necessary
No Coin-Cell: 3.3V S
Coin-Cell & No G3Hot: 3.3V S
NOTE: 30 PPM crystal required
APN 197S
at least S4. Both issues to be
complicates VDD_25M power, forcing
1.2V VDDIO. Redwood Ridge also
edge on 25MHZ_B when powered from
NOTE: SLG3NB148A provides slow rising
NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.
VDDIO_25M_B: Camera power rail for XTAL circuit.
VDDIO_25M_A: SB power rail for XTAL circuit.
VDDIO_25M_C: Thunderbolt power rail for XTAL circuit.
(SLG3NB148C).
addressed in upcoming part
SB XTAL Power
GreenClk 25MHz Power
TBT XTAL Power
Camera XTAL Power
86186 5%
MF-LF1/16W 402
XDP
PLACE_NEAR=U1100.E44:6.35mm
1/20W MF 201
5%
PLACE_NEAR=U1100.D44:6.35mm
1/20W MF 201
5%
8811
49 83 88
40 88
8811
11 88
PLACE_NEAR=U1100.A40:6.35mm MF
1/20W 201
5%
8811
5%^0
OMIT
1/16WMF-LF 402
SILK_PART=SYS RESET
5%1/16W 402
4.7K
MF-LF
12 40 83 88
11 87
11 87
28 87
402
CERM
10%6.3V
1UF
1UF
402-
10V 10V10%X5R 402
CERM
20%
0.1UF 0.1UF
402
CERM10V
20%
402
1/16WMF-LF
1M
NO STUFF
5%
0.1UF
20%10V CERM 402
1/16W MF-LF 402
5%
0402 C0G-CERM50V
12PF
5%
C0G-CERM
50V
12PF
0402
5%
4140
1K
MF
1/20W 201
5%
100K
MF
1/20W 201
5%
11 88
36 87
SOT-
DMN5L06VK-
SOT-
DMN5L06VK-
NO STUFF
MF 0201
1/20W
12 88 12 83 88
1K
1/16W MF-LF 402
5%
57 12 18 40 83 88
83654018 SOT
PLACE_NEAR=U1100.AD7:7MM
CKPLUS_WAIVE=UNCONNECTED_PINS
CKPLUS_WAIVE=UNCONNECTED_PINS
74LVC2G08GT/S
74LVC2G08GT/S SOT
2.0K
1/16WMF-LF 402
5%
20%10V CERM 402
0.1UF
BYPASS=U1950:5MM
41403029
1/20W MF
5%^0
0201
CRITICAL
TQFN
SLG3NB148CV
25.000MHZ-20PPM-12PF-85C
3.2X2.5MM-SM
CRITICAL
Chipset Support
SYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/
=PP3V3_S0_SB_PM
=PP3V3_S0_SB_PM
PM_SYSRST_L
=PP3V42_G3H_PCHPWRGD
PM_PCH_PWROK
MAKE_BASE=TRUE
XDP_DBRESET_L
PM_PCH_APWROK
CPUVR_PGOOD SYS_PWROK_R PM_PCH_SYS_PWROK
ALL_SYS_PWRGD
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
PCH_CLK33M_PCIIN
LPC_CLK33M_SMC_R
LPC_CLK33M_LPCPLUS_R
PCH_CLK33M_PCIOUT
=PP5V_S0_PCH
=PP3V3R1V5_S0_PCH_VCCSUSHDA
HDA_SDOUT_R
SPI_DESCRIPTOR_OVERRIDE
SPI_DESCRIPTOR_OVERRIDE_L
SPI_DESCRIPTOR_OVERRIDE_LS5V
=PPVBAT_G3_SYSCLK
=PP3V3_S5_SYSCLK
=PPVRTC_G3_OUT
=PP3V3_S4_SYSCLK
=PPVDDIO_S0_SBCLK
=PPVDDIO_S3RS0_CAMCLK
=PPVDDIO_TBTLC_CLK
SYSCLK_CLK25M_X
SYSCLK_CLK32K_RTC
SYSCLK_CLK25M_X2_R
SYSCLK_CLK25M_SB
SYSCLK_CLK25M_CAMERA
SYSCLK_CLK25M_X2 SYSCLK_CLK25M_TBT
SMC_DELAYED_PWRGD
PM_S0_PGOOD
R 1 2
R 1 2
R 1 2
R 1 2
R
1
2
(^1) R
2
(^1) C
2
C1902 1
2
C1920 1
2
C1922 1
2
(^1) R
2
C1924 1
2
R 1 2
C
2 1
C 1 2
(^1) R
2
(^1) R
Q1920 2
3
5
4
Q1920 6
(^2 )
R
2
1 R U1950^1
5
6 4
8 3
U
1
2 4
8 7
R1950^1
2
(^1) C
2 R
1
2
U
9 8 15
12
7101617
5 13
11 6 14
1
4
3
Y 2 4
1
3
dvt
051-
6.0.
19 OF 119
19 OF 94
2
8119
8119
81
81
811715
81
81
81
81
81 35 81
OUT
OUT
OUT
OUT
OUT
G
D S
G
D S
OUT
IN OUT IN
IN OUT
OUT
IN
IN
OUT
OUT IN IN
OUT OUT
IN
OUT
IN
OUT
OUT
OUT
IN
OUT
GND
1Y
VCC
1A
3Y 3A
2A 2Y
Y B
A
OUT IN
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN G SYM_VER_
D
S
OUT
IN
IN
08
Y
Y
GND
B
VCC
A
B
A
OUT
OUT
Apple Inc.
THEPROPRIETARY INFORMATION CONTAINED PROPERTY OF APPLE HEREIN INC. IS THE
B
D
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
D
A
C
PAGE TITLE
SHEET IV ALL RIGHTS RESERVED
R
D
DRAWING NUMBER SIZE
REVISION
BRANCH
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
HDMI HPD pull-down
RR output is open-drain, no isolation necessary
TBTLC can be on when S0 is off, and vice-versa
Redwood Ridge JTAG Isolation
Redwood Ridge Support
Buffered
TBT_PWR_EN must be high for JTAG Programming
RAM Configuration Straps
GPIO Glitch Prevention
RIO SD Card Reader Support
GS3 Connector Support
DEVSLP not supported on LPT-H
PCH 33MHz Clock for DPMUX
Pull-up values TBD
To/From RR
(Pull-ups on PCH page)
Unbuffered
LCD HPD Inverter Platform Reset Connections
(Pull-Up on CPU Page)
To/From PCH
U2060 supports I/O’s powered when VCC=0V
Isolation ensures no leakage to RR or PCH
To/From PCH
From RIO Connector
Flexible I/O Aliases
Must pull signal correctly even if always USB or PCIe
Flexible I/O Configuration Strap
SD Card Reader is always USB3 in this implementaton.
18
14
18
14
14
RAMCFG0:L
1K
5% 1/20WMF 201
1/20WMF
5%
1K
RAMCFG1:L
201
1K
5% 1/20WMF
RAMCFG2:L
201
RAMCFG3:L
1K
5% MF1/20W 201
DMN5L06VK-
SOT-
DMN5L06VK-7SOT-
10K
MF
1/20W5% 201
34
201
470K
1/20W^ 5% MF
13 20 28 83494012
201
1/20WMF
5%
10K
28 14
14
201
1/20W5% MF
100K
13
13
13
13 78 83 88 78 83 88
78 83 88 78 83 88
14
14
14
28
201 MF
1/20W5%
10K
28
28
201
10K
5%1/20W 201 MF MF
1/20W5%
10K
78 83
10%
0.1UF
X5R-CERM^ 16V 0201
201
100K 5%
1/20WMF
7978
CRITICAL
X2SON
SN74AUP3G07DQER
CRITICAL
TC7SZ08FEAPE SOT
402
20%10V CERM
0.1UF
79
1/20W MF
5% 201
PLACE_NEAR=U1100.B42:6.35MM
8411
1/16WMF-LF 402
5%
79
5% 402
100K
1/16W MF-LF
CRITICAL
SC70-HF
MC74VHC1G
402
1/16WMF-LF
5%
1/16W MF-LF 402
5%
MF-LF1/16W
402
5%
MF-LF
1/16W 402
5%
10%
0.1UF
CERM-X5R 0201
6.3V
201
470K
5% 1/20WMF
83211812
1/16W
5% MF-LF 402
5% 402
MF-LF1/16W
5% MF-LF 402 1/16W
35
28
33
34
22
88
40
49 83
79 DMN32D2LFB
DFN1006H4-
5
1814
2820
CRITICAL
74LVC2G08GT/S
SOT
16V 0201 X5R-CERM
0.1UF 10%
28
42
SYNC_MASTER=CLEAN_J45 SYNC_DATE=04/26/
Project Chipset Support
SMC_PME_SDCONN_L
=PP3V3_S0_PCH_GPIO
DP_INT_IG_HPD
PLT_RESET_L
MAKE_BASE=TRUE
DPMUX_LRESET_L
TBT_PCIE_RESET_L
CAM_PCIE_RESET_L
AP_RESET_L
SSD_RESET_L
MAKE_BASE=TRUE
PLT_RST_BUF_L
=PP3V3_S0_RSTBUF
LPC_PWRDWN_L
TBT_PWR_EN_PCH
JTAG_ISP_TCK
TBT_PWR_EN JTAG_TBT_TCK
TBT_PWR_EN
MLB_RAMCFG
MLB_RAMCFG
MLB_RAMCFG
MLB_RAMCFG
=PP3V3_S0_PCH_GPIO
SSD_DEVSLP
TP_PCI_CLK33M_OUT
LPC_CLK33M_DPMUX_UC_R
MAKE_BASE=TRUE
LPC_CLK33M_DPMUX_UC
MAKE_BASE=TRUE
TBT_CIO_PLUG_EVENT_L
HDMI_HPD
PP3V3_TBTLC
LPC_RESET_L
=PP3V3_S4_SMC
LPCPLUS_RESET_L
MAKE_BASE=TRUE
PCA9557D_RESET_L
SMC_LRESET_L
DP_IG_A_HPD_L
SD_SEL_PCIE_L_USB_H
USB3RPCIE_SD_R2D_C_N
USB3RPCIE_SD_D2R_N
USB3RPCIE_SD_R2D_C_P
USB3_SD_R2D_C_N
MAKE_BASE=TRUE
USB3_SD_D2R_P
MAKE_BASE=TRUE MAKE_BASE=TRUE
USB3_SD_D2R_N
SMC_PME_SDCONN
=TBT_CIO_PLUG_EVENT_ISOL
JTAG_ISP_TDI JTAG_TBT_TDI
JTAG_ISP_TDO JTAG_TBT_TDO
JTAG_TBT_TMS_PCH
=PP3V3_S0_PCH_GPIO
JTAG_TBT_TMS
USB3RPCIE_SD_D2R_P
=PP3V3_S0_PCH_GPIO
USB3_SD_R2D_C_P
MAKE_BASE=TRUE
SDCONN_STATE_CHANGE_L
=PP3V3_S3_SDBUF
RIO_SDCONN_STATE_CHANGE_L
Q
3
5
4
R2040^1
2
C2080 1
2
(^1) R
2
U
3
2
1 4
5
R 1 2
R 1 2
R 1 2
R 1 2
C2030 1
2
(^1) R
2
R 1 2
R 1 2
R 1 2 Q
3
1
2
U
1
5
2
6
4
8
7
3
(^1) C
2
R2002^1
2
(^1) R
2
R2012^1
2
(^1) R
2
Q
6
2
1
R2070^1
2
R2075^1
2
R2030^1
2
(^1) R
2
(^1) R
2
R2061^1
2
C2060 1
2
R
1
2
U
1
3
6
4
8
7
5
2
U
2
1 3
5
4
R 1 2
R 1 2
dvt
051-
6.0.
20 OF 119
20 OF 94
812920141211
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812920141211
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814241
812920141211
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