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LVDS Owner’s Manual
Including High-Speed CML and Signal Conditioning
High-Speed Interface Technologies
Overview 9-
Network Topology 15-
SerDes Architectures 19-
Termination
and Translation 31-
Design and
Layout Guidelines 39-
Jitter Overview 47-
Interconnect Media and
Signal Conditioning 59-
I/O Models 77-
Solutions for Design
Challenges 83-
www.ti.com/LVDS 2008
- Introduction ..........................................................................
- High-Speed Interface Technologies Overview..............
- 1.1 Differential Signaling Technology.......................................
- 1.2 LVDS – Low-Voltage Differential Signaling
- 1.3 CML – Current-Mode Logic
- 1.4 Low-Voltage Positive-Emitter-Coupled Logic
- 1.5 Selecting An Optimal Technology
- Network Topology .............................................................
- 2.1 Point-to-Point
- 2.2 Multipoint / Multidrop..........................................................
- 2.3 SerDes Architectures...........................................................
- 2.4 Mixing Signaling Technologies
- 2.5 Selecting an Interface Technology
- SerDes Architectures .......................................................
- 3.1 Introduction............................................................................
- 3.2 Parallel Clock SerDes..........................................................
- 3.3 Embedded Clock (Start-Stop) Bits SerDes
- 3.4 8b/10b SerDes
- 3.5 FPGA-Attach SerDes
- 3.6 Applications...........................................................................
- Parallel Clock SerDes
- Embedded Clock (Start-Stop) Bits SerDes
- 8b/10b SerDes
- FPGA-Attach SerDes
- 3.7 Comparison Overview..........................................................
- 3.8 Summary
- Termination and Translation............................................
- 4.1 Terminations and Impedance Matching...........................
- 4.2 Multidrop and Multipoint
- 4.3 AC Coupling
- 4.4 DC Balance
- Selecting a Capacitor.....................................................
- 4.5 Translation
- 4.6 Failsafes
- M-LVDS Failsafes
- Design and Layout Guidelines ........................................
- 5.1 PCB Transmission Lines
- 5.2 Transmission Loss
- 5.3 PCB Vias
- 5.4 Backplane Subsystem
- 5.5 Decoupling
- Jitter Overview ..................................................................
- 6.1 Introduction............................................................................
- Random Jitter Characteristics......................................
- Deterministic Jitter.........................................................
- Duty Cycle Distortion......................................................
- Inter-Symbol Interference
- Periodic Jitter
- 6.2 Additional Jitter Sources
- Effect of Input Capacitance
- FEXT/NEXT
- Systems Susceptible to Crosstalk
- Bit Error Rate
- 6.3 Pattern Dependencies and Eye Diagrams........................
- Eye Masks
- Bathtub Curves and Eye Contours
- Interconnect Media and Signal Conditioning ..............
- 7.1 Physical and Electrical Cable Characteristics
- 7.2 Signal-Conditioning Characteristics
- Media Losses in Cables and PCB Traces
- Pre-Emphasis and De-Emphasis Drivers
- Equalization
- Two Types of Equalizer Circuits
- Passive: Power-Saver Equalizers
- Active Equalizers
- Fixed Equalizers
- Variable Equalizers Allow Control...............................
- Adaptive Equalizers
- Crosstalk
- Reflections
- www.ti.com/LVDS
- 7.3 Using Pre- and De-Emphasis and Equalizers Together Contents
- 7.4 Random Noise
- 7.5 Re-clocking Receivers (Re-clockers)............................... - (Random and Deterministic) 7.6 Bit Error Rate (BER) and Jitter - Lossy Media Compensated by Equalization............... - Pre-Emphasis Eye Diagrams - PE/EQ Combination
- Semiconductor I/O Models ..............................................
- 8.1 Input/Output Buffer Information Specification
- 8.2 Behavioral Diagram of IBIS
- 8.3 3-State Output Model
- 8.4 Creating IBIS Models
- 8.5 Scattering Parameters (S Parameters)
- 8.6 SPICE Models
- Solutions for Design Challenges ....................................
- 9.1 Clock Distribution and Signal Conditioning - Point-to-Point Clock Distribution................................. - Multipoint Clock Distribution - Clock Conditioners
- 9.2 System Clock Distribution................................................... - ATCA-Synchronization Clock Interface - MicroTCA-Synchronization Clock Interface..............
- 9.3 Complementing FPGA Performance - Extending SerDes Enables FPGAs - Load Capacitance is Critical......................................... - LVDS Translation
- 9.4 Broadcast Video....................................................................
- 9.5 Extending the Reach of SerDes.......................................... - Identifying Cable-Extender-Chipset Benefits - Typical Transmission Distance Gains - Extending Signal Transmission with Conditioning. - Power-Saver Equalizers - to RS-485............................................................................... 9.6 M-LVDS: A High-Speed, Short-Reach Alternative - 9.7 Redundancy - 9.8 Testability of High-Speed Differential Networks - Functional Testing - Loopback - 9.9 DVI / HDMI............................................................................ - High Data Rates and Longer Cost-Effective Cables - Dielectric Losses Compensation for Skin Effects and - Appendix of Technical References .............................. - 10.1 Websites and LVDS Applications - 10.2 Analog Edge® and Signal Path Designer® Articles - 10.3 Outside Publications - 10.4 Application Note References - 10.5 Index - 10.6 Acronyms - 10.7 Glossary of Common Datasheet Parameters
www.ti.com/LVDS^7
Introduction
N
ational Semiconductor’s LVDS Owner’s Manual, first published in spring 1997, has been the industry’s “go-to
design guide” over the last decade. The owner’s manual helped LVDS grow from the original IEEE 1596.3-
Standard for Low-Voltage Differential Signaling (LVDS) for Scalable Coherent Interface (SCI) into the workhorse
technology it is today.
LVDS is now pervasive in communications networks and used extensively in applications such as laptop computers, office
imaging, industrial vision, test and measurement, medical, and automotive. It provides an attractive solution - a small-swing
differential signal for fast data transfers at significantly reduced power and with excellent noise immunity. Along with the
applications, LVDS continued to evolve over the last decade to meet specific requirements such as Bus LVDS and Multipoint
LVDS. For example, the latest LVDS products are capable of data rates in excess of 3 Gbps while still maintaining the low
power and noise immunity characteristics.
Today, many applications require even faster data rates and longer transmission paths. Therefore, designers should consider
technologies such as Current-Mode Logic (CML) and signal conditioning for both LVDS and CML. That is why this new
Fourth Edition includes practical design techniques for these technologies as well as LVPECL and LVCMOS.
This owner’s manual provides useful and current information. It begins with a brief overview of the three most common
high-speed interface technologies (LVDS (with variants B-LVDS and M-LVDS), CML, and LVPECL) a review of their
respective characteristics, and a section on selecting the optimal technology for an application. The manual then covers
relevant topics such as level translation, jitter, signal conditioning, and suggested design approaches. This practical informa-
tion will help you select the right solution for today’s interface design issues.
A typical LVDS driver – receiver pair is shown in Figure 1-1. A (nominal) 3.5 mA current source is located in the driver.
Since the input impedance of the receiver is high, the entire current effectively flows through the 100Ω termination resulting
in a (nominal) 350 mV voltage across the receiver inputs. The receiver threshold is guaranteed to be 100 mV or less, and this
sensitivity is maintained over a wide common mode from 0V to 2.4V. This combination provides excellent noise margins
and tolerance to common-mode shifts between the driver and receiver. Changing the current direction results in the same
amplitude but opposite polarity at the receiver. Logic ones and zeros are generated in this manner. CML and LVPECL have
a similar architecture but with different strength current sources and termination schemes.
Figure 1-2. Differential Signaling
From this simple diagram in Figure 1-2 , the advantages common to all differential signaling technologies can be seen.
First, note that the current source is always on and routed in different directions to drive logic ones and zeros. This always-
on characteristic eliminates the switching-noise spikes and EMI resulting from turning high-current transistors on and off
(as required in single-ended technologies). Secondly, the two lines of the differential pair are adjacent to each other providing
a considerable amount of noise immunity. Noise from crosstalk or EMI that is absorbed in one of the pair will also appear
in the adjacent line. Since the receiver responds to the difference between the two channels, “common-mode” noise that
appears on both lines of the pair will cancel at the receiver. Also, as the two adjacent lines carry equal current, but in opposite
directions, EMI generation is minimized.
1.2 LVDS – Low-Voltage Differential Signaling
The 350 mV typical signal swing of LVDS consumes only a small amount of power and therefore LVDS is a very efficient
technology, delivering performance at data rates up to 3.125 Gbps. The simple termination, low power, and low noise
generation generally make LVDS the technology of choice for data rates from tens of Mbps up to 3 Gbps and beyond.
Figure 1-3. Typical Data Rates and Cable Drive Strength
V-
Output Swing VOD
V+
1 0 1
1
2
3
4
56
7
0
10
0 2 4 6 8 10 12 14 16 18 20 (m) 0 1 2 3 4 5 6 7 8 9 10 (m) Lossy Cable
Low Loss Cable (in) (cm) FR-
National’s Signal Conditioners
Data Rate (Gbps)
0 15 30 45 60 0 30 60 90 120 150
LVDS LVDS with
Signal Conditioning
CML CML
with SignalConditioning
B-LVDS
M-LVDS
www.ti.com/LVDS^11
For higher data rates, technologies such as CML or LVPECL are required. As shown graphically in Figure 1-3 and 1-6 ,
CML and LVPECL are capable of very high data rates in excess of 10 Gbps. Achieving these very high data rates requires
extremely fast, sharp-edge rates and typically a signal swing of approximately 800 mV. For these reasons, CML and LVPECL
generally require more power than LVDS.
Sharp, fast edge rates include a significant amount of very-high-frequency content – and since transmission loss in cables
and FR4 traces increases with frequency, these technologies often require signal conditioning when driving long cables or
traces. See Interconnect Media, page 59 , for a more thorough discussion on signal attenuation and distortion in various
cables and other media, including various signal-conditioning techniques such as pre-emphasis and equalization that help
mitigate the effect of signal distortion in cables and traces.
1.3 CML – Current-Mode Logic
CML is a high-speed point-to-point interface capable of data rates in excess of 10 Gbps. As shown in Figure 1-4 , a common
feature of CML is that termination networks are integrated typically into both drivers and receivers. CML uses a passive
pull-up to the positive rail, which is typically 50Ω. Most implementations of CML are AC coupled, and therefore require
DC-balanced data. DC-balanced data tests require data coding that contain, on average, an equal number of ones and zeros.
(See DC Balance, page 33 ).
Figure 1-4. Typical CML Implementation
V CC
(^5050)
Differential Zo = 100Ω
High-Speed Interface Technologies Overview
www.ti.com/LVDS^13
LVDS is the most common differential signaling interface. The low power consumption, minimal EMI, and excellent
noise immunity are the features that have made LVDS an interface of choice for many applications. In addition, the LVDS
wide-input common mode makes LVDS devices easy to interoperate with other differential signaling technologies. The
latest generation of LVDS operates from DC to as high as 3.125 Gbps, allowing many applications to benefit from LVDS.
These multi-gigabit LVDS devices feature pre-emphasis and equalization that enables signal transmission over lossy cables
and printed circuit board (PCB) traces.
Applications requiring data rates greater than 3.125 Gbps will likely require CML signaling. In addition, certain communica-
tion standards (e.g. PCIe, SATA, and HDMI) mandate the use of specific signaling technologies or describe a set of conditions
such as signal amplitude and reference to VCC, consistent with CML.
For applications with data rates between 2 Gbps and 3.125 Gbps, the optimum choice will depend on the desired func-
tionality, performance, and power requirements. For relatively short distance transmission where signal conditioning is not
required the device power and jitter dominate, with CML generally having the lowest jitter and LVDS the lowest power.
For long-reach requirements, losses in the media dominate and the best choice is generally the device with the best signal-
conditioning solution for the data rate and media. Both LVDS and CML use techniques such as equalization and pre-
emphasis or de-emphasis, see Signal-Conditioning Characteristics, page 63. Understanding the loss characteristics of the
transmission media and the best signal-conditioning solution will enable the user to select the appropriate device.
Figure 1-6. Typical Application Targets for Three Common Differential Signaling Technologies
10 0M 1G 2G 3G 4G 5G 10G
LVDS
Max Data Rate (bps)
Power
Consumption
LVPECL (for data and clocks)
CML
High-Speed Interface Technologies Overview
2.2 Multipoint / Multidrop
Unlike point-to-point topologies, multipoint topologies have multiple signal drivers and receivers all sharing a single
interconnect. A variant of the multipoint topology where there is a single driver and multiple receivers is referred to as
a “multidrop’ topology ( Figure 2-2 ).
Figure 2-2. A Multidrop Topology
Figure 2-2 illustrates a typical multidrop topology. Terminating the signal bus on the far receiver side is advisable only when
the signal driver is on the opposite end of the bus from the terminated receiver. In all other cases (e.g. driver connected to
the middle of the bus), the bus needs to be terminated at both ends of the bus.
Another frequently implemented variant of the multipoint topology is “half-duplex” topology ( Figure 2-3 ) which consists of
two driver/receiver pairs that transmit and receive signals between two points over a single interconnect.
Figure 2-3. A Half-Duplex Topology
Minimize Stub
Lengths
Minimize Stub
Lengths
≈100Ω
Driver
Receiver Receiver
Receiver
- + – + –
Driver
Minimize
Stub
Lengths
Minimize
Stub
Lengths
Receiver
Receiver
Driver
www.ti.com/LVDS^17
Physical connection of multiple drivers and receivers to a common signal bus presents unique challenges to successful
multidrop-topology designs. The major challenge that system designers encounter are the impedance discontinuities that
device loading and device connections (stubs) introduce on the common bus. Matching the impedance of the loaded bus
and using signal drivers with controlled signal edges are the keys to error-free signal transmissions in multipoint topologies.
Two versions of LVDS have been optimized for multipoint: Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS).
B-LVDS shares many of the characteristics of LVDS but has much higher current drive (10 mA typical) and controlled
(slower) edge rates. B-LVDS is designed specifically for driving multiple loads and in a well-designed backplane can support
up to 32 loads. B-LVDS-controlled edge rates help reduce reflections in multidrop configurations with multiple loads and
associated stubs. The slower edges limit B-LVDS to slower data rates, typically below 1 Gbps.
The growth of B-LVDS in multidrop applications prompted the creation of an industry standard for an optimized version
of LVDS intended for such networks. National Semiconductor co-authored the standard that became TIA/EIA-899 and the
technology Multipoint LVDS (M-LVDS). M-LVDS includes all of the desirable attributes for multidrop including increased
drive, slow controlled edges, tighter input thresholds, and a wider common mode. M-LVDS is capable of driving 32 loads at
speeds up to 250 Mbps.
2.3 SerDes Architectures
Two obvious ways to add bandwidth are to either increase the bus speed or add parallel channels. Prior to the advent of
high-speed interface, the latter approach was often selected, resulting in very wide Low-Voltage Transistor-to-Transistor
Logic (LVTTL) buses and backplanes. The technique of combining slower LVTTL signals into a single-bit stream (serial-
izer), transporting the data at high speed and then redistributing at the receiver (deserializer), is very common and often
referred to as Serializer/Deserializer (SerDes). The different SerDes architectures and advantages of each are covered in the
SerDes Architectures Section on page 19.
2.4 Mixing Signaling Technologies
It is quite common for hardware platforms to have multiple signaling requirements for clocks, data, and control signals.
In modular systems, card-to-card or box-to-box communication may involve different vendors and technologies. For
these reasons, LVDS, LVPECL, and CML often coexist in the same platform, and translation between different signaling
technologies is a necessary component of system design.
One approach to simplify translation is to AC couple the two networks using capacitors in each of the differential channels.
This technique eliminates DC offsets and threshold differences, however AC coupling requires DC-balanced data. For
non-DC-balanced data, various termination networks allow translation between technologies. For a full discussion on
translation networks, see Termination and Translation, page 31.
2.5 Selecting an Interface Technology
The selection of an interface device or technology is an important one. Error-free and reliable signal transmission is a critical
component of many systems. The first decisions are often the topology: Will the network be point-to-point or multidrop?
Will SerDes be required? Bandwidth, power, and jitter budgets then need to be considered.
LVDS is the most common high-speed interface and has the dual advantages of low power and wide common mode.
LVPECL generally uses additional power but supports very high data rates with excellent jitter. CML devices offer similar
performance to LVPECL and have the advantage of a simple and usually integrated termination.
Network Topology
www.ti.com/LVDS^19
3.1 Introduction
Serial interconnects form the critical backbone of modern communications systems. The selection of the most appropriate
Serializer/Deserializer (SerDes) will have a substantial impact on system cost and performance. While the maze of choices
may seem confusing at first, SerDes devices fall into a few basic architectures, each tailored to specific application require-
ments. A basic understanding of the architectural differences enables the designer to quickly find the right SerDes for the
application. In this section, four distinct SerDes architectures are examined and the vital role each fills in system design.
3.2 Parallel Clock SerDes
Figure 3-1. Parallel-Clock-Serializer Coding Example
Parallel clock SerDes are used normally to serialize “data-address-control” parallel buses such as PCI, UTOPIA, processor
buses, and control buses. Rather than tackling the entire bus with one multiplexer, the parallel-clock-SerDes architecture
employs a bank of n-to-1 multiplexers, each serializing its section of the bus separately. The resulting serial-data streams
travel to the receiver in parallel with an additional clock-signal pair that the receiver uses to latch in and recover the data.
Since clock and data travel on multiple pairs, pair-to-pair skew must be minimized for proper deserialization.
7: Mux
LVTTL DS90CR217 LVDS
1 2 3 7
7: Mux
8 9 10 14 Input Latch
7: Mux
15 16 17 21
PLL
7 6 5 4 3 2 1
14 13 12 11 10 9 8
21 20 19 18 17 16 15
SerDes Architectures
3.3 Embedded Clock (Start-Stop) Bits SerDes
Figure 3-2. 18-bit Embedded-Clock-Bits-Serializer Coding Example
The embedded-clock-bits-architecture transmitter serializes the data bus and the clock onto one serial-signal pair. Two clock
bits, one low and one high, are embedded into the serial stream every cycle, framing the start and end of each serialized
word (hence the alternative name “start-stop bits” SerDes) and creating a periodic rising edge in the serial stream. One
benefit of this architecture is data-payload word widths are not constrained to byte multiples; 10-, 16-, 18-, and 24-bit
widths are popular bus widths.
Figure 3-3. Periodic Embedded-Clock Transition
Upon power-up, the deserializer automatically searches for the periodic embedded-clock rising edge. Since the data-payload
bits change value over time while the clock bits do not, the deserializer is able to locate the unique clock edge and synchronize.
Once locked, the deserializer recovers data from the serial stream regardless of the payload-data pattern. This automatic
synchronization capability commonly is called “lock to random data” and requires no external system intervention. This is
an especially useful feature in systems where the receiver is in a remote module not under direct system control. Since the
receiver is locked to the incoming embedded clock and not to an external reference clock, jitter requirements for both
transmitter and receiver input clocks are relaxed significantly.
Input Latch
Mux
LVTTL DS92LV18 LVDS
1
C0 C
2 3 4 18
18 C0 C1 1 2 3 4 18 C0 C
DATA DATA DATA DATA
Periodic
Embedded-Clock Transition
