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Department of Electrical Engineering
Faculty Member:Sir Sikandar Hayat Dated: 04-02-
Semester: 2nd
Lab Engineer : Ma`am Qurat UL Ain Section: BESE-10A
EE-241: Digital Logic Design
Lab 03:Digital Design of Simple Practical Circuits Group No. 9 CLO4/PLO4 CLO4/PLO5 CLO6/PLO8 CLO7/PLO Name Reg. No Viva / Quiz / Lab Performa nce Analysis of data in Lab Report Modern Tool Usage Ethics and Safety Individual and Team Work 5 Marks 5 Marks 5 Marks 5 Marks 5 Marks Mohammad Anas 290831 Zain Mushtaq Ahmad Mushtaq 287200 283632
Lab No 3 : Digital Design of Simple Practical Circuits and
Verilog Dataflow Modeling
Dataflow Modeling:
Designers can design more effectively if they concentrate on implementing the function at a level of abstraction higher than gate level. Dataflow modeling provides a powerful way to implement a design. Verilog allows a circuit to be designed in terms of the data flow between registers and how a design processes data rather than instantiation of individual gates. Dataflow modeling in Verilog allows a digital system to be designed in terms of it's function. Dataflow modeling utilizes Boolean equations, and uses a number of operators that can apply on inputs to produce outputs operators like +, - , & , !, ~ , etc. Boolean equations are used in place of logical gates’ modules. Some of the dataflow operators are shown below in modules.
Continuous Assignment:
A continuous assignment is used to drive a value onto a net/ input port/ output port. A continuous assignment statement starts with the keyword assign. The keyword assign declares a continuous assignment that binds the Boolean expression on the right-hand side (RHS) of the statement to the variable on the left-hand side (LHS). Verilog arithmetic and logical operations can be used in assign .The syntax of assign is as follows:
assign <net_name> = ;
assign out = in1 & in2;
module test(out1,out2,in1,in2); input in1,in2; output out1,out2; wire w1,w2,w3,w4; assign w1= ~in1;
assign w2= ~in2; assign w3= w1 & in2; assign w4= in1 & w2; assign out2= in1 & in2; assign out1= w3 | w4; endmodule module lab3; reg in1,in2; wire out1,out2; test t1(out1,out2,in1,in2); initial begin $monitor ("t=%t,a=%b,b=%b,sum=%b,carry=%b", $time,in1,in2,out1,out2); #100 in1=1'b0;in2=1'b0; #100 in1=1'b0;in2=1'b1; #100 in1=1'b1;in2=1'b0; #100 in1=1'b1;in2=1'b1; end endmodule Design the following three practical circuits , by giving the truth table of the problem and then giving the circuit for the design. Practically demonstrate the
A B C Output ((A&B)&C) 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 Task No 3 Design a three-way switch for lighting a bulb. Suppose the Switch A is installed at the enterance of the room, switch B is installed to the debside table. Now three way switching can facilitate the switching ON/OFF from any location. The machanism is such that if a single switch is on the bulb should be ON. Now if the second switch is turned on the bulb if switched on earlier is switched off. If two switches are already on and third switch is turned on then it should switch on the bulb. Draw its truthtable. Implement with basic gates.
inputs and outputs are coded ( in terms of binary values ) and complete the truth table for the system. Suppose A and B are inputs from car speed A B Speed 0 0 Under 45 0 1 Between 46 and 55 1 0 Between 56 and 65 1 1 Over 65 Suppose C and D are inputs from speed limit C D Speed Limit 0 0 45 0 1 55 1 0 65 1 1 X F indicates whether the car is going above the speed limit. And G indicates that the car is driving at “dangerous speed” – defined as either over 65 MPH or more than 10 MPH above the speed limit A B C D F G 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 1
