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Department of Electrical Engineering
Faculty Member: Miss Quratulain Dated:11-02- Semester: 2nd Section: BESE-10A
EE-221: Digital Logic Design
Lab 04: Implementation of Digital Circuits
PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO Name Reg. No Viva / Lab Performanc e Analysis of data in Lab Report Modern Tool Usage Ethics and Safety Individual and Team Work Total marks Obtained 5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks Mohammad Anas 290831 M Ahmed Mushtaq 283632 Group No.: 22
Lab 4: Implementation of Digital Circuits
Lab Instructions This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab Viva session. The lab report will be uploaded on LMS three days before scheduled lab date. The students will get hard copy of lab report, complete the Pre-lab task before coming to the lab and deposit it with teacher/lab engineer for necessary evaluation. Alternately each group to upload completed lab report on LMS for grading. The students will start lab task and demonstrate design steps separately for step-wise evaluation (course instructor/lab engineer will sign each step after ascertaining functional verification) Remember that a neat logic diagram with pins numbered coupled with nicely patched circuit will simplify trouble-shooting process. After the lab, students are expected to unwire the circuit and deposit back components before leaving. The students will complete lab task and submit complete report to Lab Engineer before leaving lab There are related questions at the end of this activity. Give complete answers. . This Lab has been divided into two parts. The first part is the hardware implementation of a digital circuit. In next part you will simulate the same circuit using Verilog. Objectives: Simulate Basic Circuits using Verilog Hardware Implementation of Basic Logic Circuits
Circuit Schematic 1:
In this circuit, we used Inverters (7404), 2-input OR Gate (7432), and 2-input AND Gate (7408).
Circuit Schematic 2:
In this circuit, we used Inverters (7404) (2 NOT Gates), 2-input OR Gate (7432), and 2-input AND Gates (7408) (3 AND Gates). Truth Table: A B sum Carry 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
A B C F
Lab Task 2: (4 marks) (
Marks) Write Verilog code for the circuit 1 at gate-level and perform simulation. Paste below Verilog code, stimulus, and result waveforms. Does your hardware results match with software result? If no, why module eg2(F, A, B, C); output F; input A, B, C; wire w1, w2; not n1(w1, A); or or1(w2, C, w1); and and3(F, w2, B); endmodule module eg3; reg a,b,c; wire F; eg2 temp(F,a,b,c); initial
Yes, our hardware results match with our software result.
