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Department of Electrical Engineering
Faculty Member: Miss Quratulain Dated:28-Jan- Semester: 2nd^ Section: BESE-10A Group: 22
EE-221: Digital Logic Design
Lab No # 2: Introduction to Verilog (CLO4, P3)
CLO4/PLO4 CLO4/PLO5 CLO6/PLO8 CLO7/PLO Name Reg. No Viva / Quiz / Lab Performa nce Analysis of data in Lab Report Modern Tool Usage Ethics and Safety Individual and Team Work 5 Marks 5 Marks 5 Marks 5 Marks 5 Marks Mohammad Anas 290831 Zain Mushtaq 287200 M Ahmed Mushtaq 283632
Lab2: Introduction to Verilog, Gate-level/Behavioral Modeling and Hardware
Implementation of Basic Logic Circuit
Lab Instructions This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab Viva session. The lab report will be uploaded on LMS three days before scheduled lab date. The students will get hard copy of lab report, complete the Pre-lab task before coming to the lab and deposit it with teacher/lab engineer for necessary evaluation. Alternately each group to upload completed lab report on LMS for grading. The students failing to submit Pre-Lab will not be allowed to perform Lab work. The students will start lab task and demonstrate design steps separately for step-wise evaluation( course instructor/lab engineer will sign each step after ascertaining functional verification) Remember that a neat logic diagram with pins numbered coupled with nicely patched circuit will simplify trouble-shooting process. After the lab, students are expected to unwire the circuit and deposit back components before leaving. The students will complete lab task and submit complete report to Lab Engineer before leaving lab. Verilog tutorial part is non-printable and for reference only. There are related questions at the end of this activity. Give complete answers. This Lab has been divided into two parts. In first part you will be introduced to Verilog and Gate-Level Modeling. The next part is the hardware implementation of a Boolean function given to you. Objectives: Understand HDL and compare it with normal programming languages. Simulate Basic Gates using Verilog withModelSim Write stimulus using Verilog Derive algebraic expression for a Boolean function from the given schematics. Hardware Implementationof Logic Circuit
Lab Tasks: (8 marks)
Lab Task 1: (3 marks) Write the Verilog Code using Gate Level modeling for the following circuit. List the code for design as well as stimulus below: CODE: module task1(out1,out2,IN1,IN2); input IN1,IN2; output out1,out2; wire W1,W2,W3,W4; not N1(W1,IN1); not N2(W2,IN2); and A1(W3,W1,IN2); and A2(W4,W2,IN1); or O(out1,W3,W4); and A3(out2,IN1,IN2); endmodule //test module task1; reg IN1,IN2;
wire out1,out2; task1(out1,out2,IN1,IN2); initial begin #100 IN1=1'b0,IN2=1'b0; #100 IN1=1'b0,IN2=1'b1; #100 IN1=1'b1,IN2=1'b0; #100 IN1=1'b1,IN2=1'b1; #100; end endmodule Lab Task 2 (2 marks)
endmodule //test module test; reg in1,in2; wire o1,o2; task1 t1(o1,o2,in1,in2); initial begin $monitor("t=%t,A=%b,B=%b,SUM=%b,CARRY=%b",$time,in1,in2,o1,o2); #100 in1=1'b0;in2=1'b0; #100 in1=1'b0;in2=1'b1; #100 in1=1'b1;in2=1'b0; #100 in1=1'b1;in2=1'b1; #100; end endmodule
Lab Task 3:(3 marks) After determining the function performed by the circuit given in Lab Task 1, write the Verilog description of the circuit at dataflow. Comment on the two different modeling levels you used to model the same circuit. (Paste snapshots of the codes and stimulus’s below)
