Download DLD_Lab_8_Check yourself and more Lab Reports Digital Logic Design and Programming in PDF only on Docsity!
Department of Electrical Engineering
Faculty Member:____________________
Dated:
________________
Semester:__________________________ Section: ________________
EE-221: Digital Logic Design
Lab 8: Design of a Combinational Circuit (BCD to
7-Segment Decoder)
PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO
Name Reg. No Viva / Lab
Performanc e Analysis of data in Lab Report Modern Tool Usage Ethics and Safety Individual and Team Work Total marks Obtained 5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks
Lab 8: Design of a Combinational Circuit (BCD to 7-Segment Decoder)
Group No.:
Lab Instructions This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab Viva session. The lab report will be uploaded on LMS three days before scheduled lab date. The students will get hard copy of lab report, complete the Pre-lab task before coming to the lab and deposit it with teacher/lab engineer for necessary evaluation. Alternately each group to upload completed lab report on LMS for grading. The students will start lab task and demonstrate design steps separately for step-wise evaluation( course instructor/lab engineer will sign each step after ascertaining functional verification) Remember that a neat logic diagram with pins numbered coupled with nicely patched circuit will simplify trouble-shooting process. After the lab, students are expected to unwire the circuit and deposit back components before leaving. The Total duration for the lab is 3 hrs. After lab duration, a deduction of 5 marks per day will be done for late submission. A lab with in-complete lab tasks will not be accepted. The students will complete lab task and submit complete report to Lab Engineer before leaving lab. There are related questions at the end of this activity. Give complete answers. This Lab Activity has been designed to familiarize the student withdesign and workingof a BCD to 7-Segment Decoder Objectives:
Simplification of Combinational Circuits
Design and Implementation of a BCD to 7-Segment Decoder for Selected Digit Display
Using 7-Segment LED Displays
Understanding the difference between common cathode and common anode displays
3. Complete the following table.
Inputs (Binary) Outputs(7 LEDs on 7-Segment Display) A B C D a b c d e f g 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 1 0 1 1 0 1 1 0 1 0 0 1 1 1 1 1 1 0 0 1 0 1 0 0 0 1 1 0 0 1 1
1 0 1 0 X X X X X X X
1 0 1 1 X X X X X X X
1 1 0 0 X X X X X X X
1 1 0 1 X X X X X X X
1 1 1 0 X X X X X X X
1 1 1 1 X X X X X X X
4. Design a BCD-to-Seven Segment Decoder with minimum number of gates that
coverts BCD Numbers 0 through 9 in such a way that the display shows 0-9 on
the Seven-Segment-Display. Take other combinations/numbers as don’t care
condition. For what configuration are you making truth table?
a) Give Truth Table
(1 Mark)
Inputs (Binary) Outputs(7 LEDs on 7-Segment Display) A B C D a b c d e f g 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 1 0 1 1 0 1 1 0 1 0 0 1 1 1 1 1 1 0 0 1 0 1 0 0 0 1 1 0 0 1 1
1 0 1 0 X X X X X X X
1 0 1 1 X X X X X X X
1 1 0 0 X X X X X X X
1 1 0 1 X X X X X X X
1 1 1 0 X X X X X X X
1 1 1 1 X X X X X X X
b) K-Map Simplification
K-map for “a”:
AB\CD 00 01 11 10
11 x x x x
10 1 1 x x
K-map for “b”:
AB\CD 0 01 11 10
AB\CD 00 01 11 0
1 x x x x
10 1 1 x x
K-map for “g”:
AB\CD 00 01 11 0
1 x x x x
10 1 1 x x
Expressions :
a = A + C + BD + B’D’ b = A + B’ + C’D’ + CD c = B + C’ + D d = A + B’D’ + B’C + CD’ + BC’D e = B’D’ + CD’ f = A + C’D’ + BD’ + BC’ g = A + B’C + BD’ + BC’
c) Give Logic diagram for your complete design.
end
endmodule
Waveform:
2. Mention which configuration of 7-Segment Display did you use in Lab? If you were
to use the other configuration what change would you need in your circuit?
Observations/Comments:
