Lab manual for logic design, Study Guides, Projects, Research of Digital Logic Design and Programming

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EXPERIMENT: 1 LOGIC GATES

AIM: To study and verify the truth table of logic gates

LEARNING OBJECTIVE:

• Identify various ICs and their specification.

COMPONENTS REQUIRED:

• Logic gates (IC) trainer kit.
• Connecting patch chords.
• IC 7400, IC 7408, IC 7432, IC 7406, IC 7402, IC 7404, IC 7486

THEORY: The basic logic gates are the building blocks of more complex logic circuits. These logic gates perform the basic Boolean functions, such as AND, OR, NAND, NOR, Inversion, Exclusive-OR, Exclusive-NOR. Fig. below shows the circuit symbol, Boolean function, and truth. It is seen from the Fig that each gate has one or two binary inputs, A and B, and one binary output, C. The small circle on the output of the circuit symbols designates the logic complement. The AND, OR, NAND, and NOR gates can be extended to have more than two inputs. A gate can be extended to have multiple inputs if the binary operation it represents is commutative and associative.

These basic logic gates are implemented as small-scale integrated circuits (SSICs) or as part of more complex medium scale (MSI) or very large-scale (VLSI) integrated circuits. Digital IC gates are classified not only by their logic operation, but also the specific logic-circuit family to which they belong. Each logic family has its own basic electronic circuit upon which more complex digital circuits and functions are developed. The following logic families are the most frequently used.

TTL
Transistor-transistor logic ECL
Emitter-coupled logic MOS
Metal-oxide semiconductor CMOS
Complementary metal-oxide semiconductor

TTL and ECL are based upon bipolar transistors. TTL has a well established popularity among logic families. ECL is used only in systems requiring high-speed operation. MOS and CMOS, are based on field effect transistors. They are widely used in large scale integrated circuits because of their high component density and relatively low power consumption. CMOS logic consumes far less power than MOS logic. There are various commercial

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VIVA QUESTIONS:

1. Why NAND & NOR gates are called universal gates?
2. Realize the EX – OR gates using minimum number of NAND gates.
3. Give the truth table for EX-NOR and realize using NAND gates?
4. What are the logic low and High levels of TTL IC’s and CMOS IC’s?
5. Compare TTL logic family with CMOS family?
6. Which logic family is fastest and which has low power dissipation?

EXPERIMENT: 2 REALIZATION OF A BOOLEAN FUNCTION.

AIM: To simplify the given expression and to realize it using Basic gates and Universal gates

LEARNING OBJECTIVE:  To simplify the Boolean expression and to build the logic circuit.  Given a Truth table to derive the Boolean expressions and build the logic circuit to realize it.

COMPONENTS REQUIRED: IC 7400, IC 7408, IC 7432, IC 7406, IC 7402, Patch Cords & IC Trainer Kit.

THEORY: Canonical Forms (Normal Forms): Any Boolean function can be written in disjunctive normal form (sum of min-terms) or conjunctive normal form (product of max-terms). A Boolean function can be represented by a Karnaugh map in which each cell corresponds to a minterm. The cells are arranged in such a way that any two immediately adjacent cells correspond to two minterms of distance 1. There is more than one way to construct a map with this property. Karnaugh Maps

For a function of two variables, say, f(x, y),

For a function of three variables, say, f(x, y, z)

For a function of four variables: f(w, x, y, z)

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Realization of Boolean expression:

1. Y= A BCD ABCD ABCD ABCD ABCD ABCD ABCD

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AB 1 1 1 1 1 1 1

After simplifying using K-Map method we get Y =A

_ B + C

_ D

Realization using Basic gates TRUTH TABLE

Realization using NAND gates

Realization using NOR gates

INPUTS OUTPUT

A B C D Y

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4. What is meant by canonical representation?
5. What is K-map? Why is it used?
6. What are universal gates?

EXPERIMENT: 3 ADDERS AND SUBTRACTORS

AIM: To realize i) Half Adder and Full Adder ii) Half Subtractor and Full Subtractor by using Basic gates and NAND gates

LEARNING OBJECTIVE:  To realize the adder and subtractor circuits using basic gates and universal gates  To realize full adder using two half adders  To realize a full subtractor using two half subtractors

COMPONENTS REQUIRED: IC 7400, IC 7408, IC 7486, IC 7432, Patch Cords & IC Trainer Kit.

THEORY: Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and B, is called a half-adder. Addition will result in two output bits; one of which is the sum bit, S, and the other is the carry bit, C. The Boolean functions describing the half-adder are: S =A ⊕ B C = A B

Full-Adder: The half-adder does not take the carry bit from its previous stage into account. This carry bit from its previous stage is called carry-in bit. A combinational logic circuit that adds two data bits, A and B, and a carry-in bit, Cin , is called a full-adder. The Boolean functions describing the full-adder are: S = (x ⊕ y) ⊕ Cin C = xy + Cin (x ⊕ y)

Half Subtractor: Subtracting a single-bit binary value B from another A (i.e. A -B ) produces a difference bit D and a borrow out bit B-out. This operation is called half subtraction and the circuit to realize it is called a half subtractor. The Boolean functions describing the half- Subtractor are: S =A ⊕ B C = A’ B

Full Subtractor: Subtracting two single-bit binary values, B, Cin from a single-bit value A produces a difference bit D and a borrow out Br bit. This is called full subtraction. The Boolean functions describing the full-subtracter are: D = (x ⊕ y) ⊕ Cin Br= A’B + A’(Cin) + B(Cin)

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I. TO REALIZE HALF ADDER

TRUTH TABLE BOOLEAN EXPRESSIONS:

S=A ⊕ B

C=A B

i) Basic Gates ii) NAND Gates

II. FULL ADDER

TRUTH TABLE BOOLEAN EXPRESSIONS:

S= A ⊕ B ⊕ C

C=A B + B Cin + A Cin

i)BASIC GATES

INPUTS OUTPUTS

A B S C

INPUTS OUTPUTS

A B Cin S C 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

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i)BASIC GATES ii) NAND Gates

IV. FULL SUBTRACTOR

TRUTH TABLE BOOLEAN EXPRESSIONS:

D= A ⊕ B ⊕ C

Br=

_ A B + B Cin +

_ A Cin

i) BASIC GATES

INPUTS OUTPUTS

A B Cin D Br 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1

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ii) To Realize the Full subtractor using NAND Gates only

PROCEDURE:

• Check the components for their working.
• Insert the appropriate IC into the IC base.
• Make connections as shown in the circuit diagram.
• Verify the Truth Table and observe the outputs.

RESULT: The truth table of the above circuits is verified.

VIVA QUESTIONS:

1. What is a half adder?
2. What is a full adder?
3. What are the applications of adders?
4. What is a half subtractor?
5. What is a full subtractor?
6. What are the applications of subtractors?
7. Obtain the minimal expression for above circuits.
8. Realize a full adder using two half adders
9. Realize a full subtractors using two half subtractors

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is 011 2. To add four bits we require four full adders arranged in parallel. IC 7483 is a 4- bit parallel adder whose pin diagram is shown.

IC 7483 pin diagram

i) 4-Bit Binary Adder

An Example: 7+2=11 (1001)

• 7 is realized at A 3 A 2 A 1 A 0 = 0111
• 2 is realized at B 3 B 2 B 1 B 0 = 0010 Sum = 1001

ADDER CIRCUIT:

MSB LSB

INPUTS

Cin A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0 OUTPUT Cout S 3 S 2 S 1 S 0

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PROCEDURE:

• Check all the components for their working.
• Insert the appropriate IC into the IC base.
• Make connections as shown in the circuit diagram.
• Apply augend and addend bits on A and B and cin=0.
• Verify the results and observe the outputs.

ii) 4-BIT BINARY SUBTRACTOR. Subtraction is carried out by adding 2’s complement of the subtrahend. Example: 8 – 3 = 5 (0101)

• 8 is realized at A 3 A 2 A 1 A 0 = 1000
• 3 is realized at B 3 B 2 B 1 B 0 through X-OR gates = 0011
• Output of X-OR gate is 1’s complement of 3 = 1100
• 2’s Complement can be obtained by adding Cin = 1

Therefore Cin = 1 A 3 A 2 A 1 A 0 = 1 0 0 0 B 3 B 2 B 1 B 0 = 1 1 0 0 S 3 S2 S1 S 0 = 0 1 0 1 Cout = 1 (Ignored)

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Code converter is a combinational circuit that translates the input code word into a new corresponding word. The excess-3 code digit is obtained by adding three to the corresponding BCD digit. To Construct a BCD-to-excess-3-code converter with a 4-bit adder feed BCD- code to the 4-bit adder as the first operand and then feed constant 3 as the second operand. The output is the corresponding excess-3 code.

To make it work as a excess-3 to BCD converter, we feed excess-3 code as the first operand and then feed 2's complement of 3 as the second operand. The output is the BCD code.

TRUTH TABLE:

i) BCD - EXCESS-3 CODE ii) EXCESS-3 TO BCD CODE

BCD EX-

0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

Circuit Diagram

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PROCEDURE:

• Check all the components for their working.
• Insert the appropriate IC into the IC base.
• Make connections as shown in the circuit diagram.
• Apply BCD code as first operand(A) and binary 3 as second operand(B) and cin=0 for

Realizing BCD-to-Excess-3-code:

• Apply Excess-3-code code as first operand(A) and binary 3 as second operand(B) and Cin=1 for realizing Excess-3-code to BCD.
• Verify the Truth Table and observe the outputs.

RESULT: Realized BCD code to Excess-3 code conversion and vice versa using 7483 IC

VIVA QUESTIONS: 1) What is the internal structure of 7483 IC?

2. What do you mean by code conversion?
3. What are the applications of code conversion?
4. How do you realize a subtractor using full adder?
5. What is a ripple Adder? What are its disadvantages?

EXPERIMENT: 6 BINARY TO GRAY CODE CONVERTER

AIM: To realize Binary to Gray code converter and vice versa.

EX-3 BCD

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BINARY TO GRAY CODE USING EX-OR GATES

REALIZATION USING NAND GATES:

II) GRAY TO BINARY CONVERSION

B3 = G

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B2=G3 ⊕ G

B1=G3 ⊕ G2 ⊕ G

B0=G3 ⊕ G2 ⊕ G1 ⊕

G

BOOLEAN EXPRESSIONS:

B3=G

B2=G3 ⊕ G

B1=G3 ⊕ G2 ⊕ G

B0=G3 ⊕ G2 ⊕ G1 ⊕ G

GRAY TO BINARY CODE CONVERSION USING EX-OR GATES

Gray Binary

G3 G2 G1 G0 B3 B2 B1 B