EDA Tools: Comprehensive Overview of Design Automation and HDL Languages, Slides of Computer Science

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EDA Tools

1. Design Entry

a. View Logic

b. Mentor Graphics (Renoir)

c. Cadence Design System

d. OrCAD

e. ALDEC (Active HDL)

f. SimuCAD (Silos-3)

EDA Tools

2.Design Simulation

a. Model Technology (Modelsim)

b.Synopsy

c. Cadence

d.SimulCAD (Silos-3)

e. Quick turn Design Systems (Power Suite)

f. View Logic (VHD Simulator)

EDA Tools

4. Programmable Logic (Vendors)

a. Xilinx – Xilinx Foundation Series b. Altera – MaxPlus II c. Altera – Quartus II Ver. 4. d. Lattice – isp Expert Compiler e. Lucent – ORCA Foundary Development f. Actel – FPGA Development System g. Cypress- Warp h. Atmel – FPGA Development System i. Quick Logic – Quick works j. Gate Field – ASIC Master

Other HDLs

1. ISPS (Instruction Set Processor

Specification)

• Behavioral Language
• Used to design software based on specific hardware
• Statement level timing control, but no gate level control

3. ZEUS

ZEUS

• Created at General Electric
• Hierarchical
• Functional Descriptions
• Structural Descriptions
• Clock Timing, but no gate delays
• No asynchronous circuits

4. TEGAS

• TEGAS (Test Generation And Simulation)
  • Structural with behavioral extension
  • Hierarchical
  • Allows detailed timing specification

6. ABEL

• ABEL
  • Simplified HDL
  • PLD Language
  • Dataflow primitives e.g. registers
  • Can use to Program Xilinx FPGA

7. AHPL

• AHPL (A Hardware Programming

Language)

• Dataflow language
• Implicit Clock
• Does not support asynchronous circuits
• Fixed data types
• Non-hierarchical

9. ALTERA

• ALTERA
  • Created by Altera Corporation
  • Simplified dialect of HDL
    • (AHDL: Altera HDL)

10. CDL

• CDL (Computer Design Language)
  • Academic Language for teaching digital systems
  • Dataflow Language
  • Non-hierarchical
  • Contains conditional statements