Data Types - Sequential Logic Design - Lecture Slides, Slides of Digital Logic Design and Programming

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Lecture

• Agenda
  1. VHDL Data Types
• Announcements
  1. n/a

Sequential Logic Design

Data Types

• Signals
  • a single bit is considered a Scalar quantity
  • a bus (or multiple bits represented with one name) is called a Vector
  • in VHDL, we can define a signal bus as:

data_bus : in bit_vector (7 downto 0); -- we will use "downto"

or

data_bus : in bit_vector (0 to 7);

• the Most Significant Bit (MSB) is ALWAYS on the left of the range description:

ex) data_bus : in bit_vector (7 downto 0);

data_bus(7) = MSB

ex) data_bus : in bit_vector (0 to 7);

data_bus(0) = MSB

Data Types

• Scalar Data Types (Built into VHDL)
  • scalar means that the type only has one value at any given time

Boolean - values {TRUE, FALSE}

• not the same as '0' or '1'

Character - values are all symbols in the 8-bit ISO8859-1 set (i.e., Latin-1)

• examples are '0', '+', 'A', 'a', ''

Integer - values are whole numbers from -2,147,483,647 to +2,147,483,

• the range comes from +/- 2 32
• examples are -12, 0, 1002

Real - values are fractional numbers from -1.0E308 to +1.0E

• examples are 0.0, 1.134, 1.0E

Bit - values {'0', '1'}

• different from Boolean
• this type can be used for logic gates
• single bits are always represented with single quotes (i.e., '0', '1')

Data Types

• Array Data Types (Built into VHDL)
  • array is a name that represents multiple signals

Bit_Vector - vector of bits, values {'0', '1'}

• array values are represented with double quotes (i.e., "0010")
• this type can be used for logic gates

ex) Addr_bus : in BIT_VECTOR (7 downto 0);

• unlimited range
• first element of array has index=0 (i.e., Addr_bus(0)…)

String - vector of characters, values{Latin-1}

• again use double quotes
• define using "to" or "downto" ("to" is easier for strings)

ex) Message : string (1 to 10) := "message here…"

• first element in array has index=1, this is different from BIT_VECTOR

STD_LOGIC Data Types

• STD_LOGIC
  • we talked about the need for realistic data types to model busses and drive strength
  • within VHDL we only have BIT and BIT_VECTOR to model logic gates
  • these don't work for the real world
  • we need to use the IEEE.STD_LOGIC_1164.ALL package

STD_LOGIC - "resolved" data type, scalar (analogous to BIT, but with drive strength)

STD_LOGIC_VECTOR

• "resolved" data type, vector (analogous to BIT_VECTOR, but with drive strength)
• we use this package by entering the following:

library IEEE; use IEEE.STD_LOGIC_1164.ALL

STD_LOGIC Data Types

• Resolution
  • These types have the following possible values

U = Un-Initialized X = Forcing Unknown 0 = Forcing '0' 1 = Forcing '1' Z = Forcing 'Z' W = Weak Unknown L = Weak '0' H = Weak '1'

• = Don't Care
• There is a table that VHDL can go to in order to "Resolve" any of the following conditions on a single line

ex) 0 and H = 0 0 and 1 = 0

• we will always use these data types (from now on, don't use BIT or BIT_VECTOR)