Structural Design - Sequential Logic Design - Lecture Slides, Slides of Digital Logic Design and Programming

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Lecture

• Agenda
  1. VHDL : Structural Design
• Announcements
  1. n/a

Sequential Logic Design

• Structural Design
  • we can specify functionality in an architecture in two ways

1. Structurally : text based schematic, manual instantiation of another system

2. Behaviorally : abstract description of functionality

• we will start with learning Structural VHDL design
• Components
• blocks that already exist and are included into a higher level design
• we need to know the entity declaration of the system we are calling
• we "declare" a component using the keyword "component"
• we declare the component in the architecture which indicates we wish to use it

• Component Example
  • let's use these pre-existing entities "xor2" & "or2"

entity xor2 is

port (In1, In2 : in STD_LOGIC; Out1 : out STD_LOGIC);

end entity xor2;

entity or2 is

port (In1, In2 : in STD_LOGIC; Out1 : out STD_LOGIC);

end entity or2;

• Component Example
  • now let's include the pre-existing entities "xor2" & "or2" into our "TOP" design

entity TOP is port (A,B,C : in STD_LOGIC; X : out STD_LOGIC); end entity TOP;

architecture TOP_arch of TOP is

component xor2 -- declaration of xor2 component port (In1, In2 : in STD_LOGIC; Out1 : out STD_LOGIC); end component;

component or2 -- declaration of or2 component port (In1, In2 : in STD_LOGIC; Out1 : out STD_LOGIC); end component;

begin …..

• Signal Syntax

architecture TOP_arch of TOP is

signal signal-name : signal-type; signal signal-name : signal-type;

• Let's put the signal declaration into our Architecture
  • now let's include the pre-existing entities "xor2" & "or2" into our "TOP" design

architecture TOP_arch of TOP is

signal node1 : STD_LOGIC;

component xor2 -- declaration of xor2 component port (In1, In2 : in STD_LOGIC; Out1 : out STD_LOGIC); end component;

component or2 -- declaration of or2 component port (In1, In2 : in STD_LOGIC; Out1 : out STD_LOGIC); end component;

begin …..

end architecture TOP_arch;

node

• Port Maps
  • There are two ways describe the "port map" of a component

1. Positional
2. Explicit

• Positional Port Map
  • signals to be connected to the component are listed in the exact order as the components port order

ex) U1 : xor2 port map (A, B, node1);

• Explicit Port Map
  • signals to be connected to the component are explicitly linked to the port names of the component using the "=>" notation (Port => Signal, Port => Signal, ….)

ex) U1 : xor2 port map (In1 => A, In2 => B, Out1 => node1);

• Execution
  • All components are executed CONCURRENTLY
  • this mimics real hardware
  • this is different from traditional program execution (i.e., C/C++) which is executed sequentially

because

We are NOT writing code, we are describing hardware!!!

• Generate Statement
  • there are times when we want to instantiate a large number of the same component (ex. on a bus)
  • VHDL has a "generate" statement that allows us to instantiate using a loop structure

syntax: label : for identifier in range generate

component instantiation

end generate;

• Generate Statement

ex) instantiate 8 inverters assuming X and Y are busses of equal width

begin

Gen1 : for i in 1 to 8 generate

U1 : INV1 port map ( In1=>X(i), In2=>Y(i) );

end generate;