VHDL Design: ALU, Clock Module, and Structural Implementation, Slides of Computer Science

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ALU Design

switches

7-segment displays

LEDs

pushbuttons

Digilab XL

library IEEE;

use IEEE.std_logic_1164. all ;

use IEEE.std_logic_arith. all ;

entity osc_4k is

port (

clk: out std_logic

end osc_4k;

Clock Module: osc_4k

architecture xilinx of osc_4k is component OSC port ( F490: out std_logic ); end component ; component BUFGS port ( I: in std_logic; O: out std_logic ); end component ; signal f: std_logic; begin xosc4: OSC port map ( f ); xbufgs: BUFGS port map ( f, clk ); end xilinx; 490 Hz

Can change to:

F

F16K

F500K

F8M

ALU Entity

library IEEE; use IEEE.std_logic_1164. all ; use IEEE.std_logic_unsigned. all ; entity alu is port ( a: in STD_LOGIC_VECTOR (7 downto 0); b: in STD_LOGIC_VECTOR (7 downto 0); sel: in STD_LOGIC_VECTOR (1 downto 0); y: out STD_LOGIC_VECTOR (7 downto 0) ); end alu;

architecture alu_arch of alu is begin alu1: process (a,b,sel) begin case sel is when "00" => -- a + b y <= a + b; when "01" => -- 1+ y <= a + 1; when "10" => -- invert y <= not a; when "11" => -- 2* y <= a(6 downto 0) & '0'; when others => null ; end case ; end process alu1; end alu_arch;

T3main.vhd

library IEEE; use IEEE.std_logic_1164. all ; entity T3main is port ( SW: in STD_LOGIC_VECTOR (1 to 8); BTN: in STD_LOGIC_VECTOR (1 to 4); LD: out STD_LOGIC_VECTOR (1 to 8) ); end T3main;

architecture T3main_arch of T3main is component mux port ( a : in std_logic_vector(7 downto 0); b : in std_logic_vector(7 downto 0); sel : in std_logic; y : out std_logic_vector(7 downto 0)); end component ; component alu port ( a : in std_logic_vector(7 downto 0); b : in std_logic_vector(7 downto 0); sel : in std_logic_vector(1 downto 0); y : out std_logic_vector(7 downto 0)); end component ;

signal tin, T, N, y: std_logic_vector(7 downto 0); signal clr, clk, clk4: std_logic; begin U0: mux2 port map (a => y, b => SW, sel => SW(1), y => tin); Treg: reg port map (d => tin, load => SW(2), clr => clr, clk =>clk, q => T); Nreg: reg port map (d => T, load => SW(3), clr => clr, clk =>clk, q => N); U1: alu port map (a => T, b => N, sel => SW(4 to 5), y => y); U2: debounce port map (inp => BTN(4), clk => clk4, clr => clr, outp => clk); U3: osc_4k port map (clk => clk4); clr <= BTN(1); LD <= T; end T3main_arch;