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OVERVIEW
Memory and data storage take many forms, even in a single computer system. Figure 6-1 classi-
fies the various memory categories that are discussed in the following pages. There are two main
classifications of memory families. These are RAM (Random Access Memory) and ROM (Read
Only Memory) devices. RAM devices are volatile, which is to say they lose their memory content
when the power to the host system is turned off. ROM devices are non-volatile, meaning they
retain their stored data when the power is removed.
RAM products are read and written to with the same electrical characteristics. They are easy to write
but are volatile, meaning that when the power is turned off, the devices lose the memory content.
ROM-based devices—ROM, EPROM, EEPROM, and flash memory devices are easy to read but
are more difficult to program (write) than RAM devices. EEPROM and flash devices are more dif-
ficult to program than they are to read. EPROMs need a mechanical step (UV-light) to erase the
memory cells prior to re-programming the device. One-time programmable (OTP) EPROMs can
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Memories
RAM
Volatile Non Volatile
Non Programmable
One-Time Programmable
Programmable Several Times
ROM
SRAM DRAM NVRAM BRAM FRAM ROM OTP EPROM EEPROM Flash Source: ICE, "Memory 1997" 19993A
Figure 6-1. Memory Classification
be written only one time by the user. ROM products are programmed during process manufac-
turing. Figure 6-2 shows the different types of memories and some of the main characteristics of
the devices.
GENERAL TECHNOLOGY ISSUES
Memory devices have historically been considered “process drivers” as well as revenue produc-
ers. A process driver is a product that is manufactured in large wafer volumes, that pushes the
state-of-the-art in processing, and has a die yield that can be used to measure the effectiveness of
the process.
6-2^ INTEGRATED CIRCUIT ENGINEERING CORPORATION
DRAM SRAM EPROM ROM Parallel Flash NVRAM FRAM EEPROM
Characteristic
Cell Organization
Storage Method
Number of Devices in Cell
Relative Cell Size
Density
Overhead Cost
Volatile (Power Off)
Data Retention (D.C. Power On)
In System Reprogrammable
Number of Reprogram Times (Endurance)
Typical Write (Reprogram) Speed
Typical Read Speed (ns)
1T + 1C
Charge on Capacitor
64Mbit
Refresh Logic
Yes
4ms
Yes
∞
100ns
100
1 Flip-Flop
Flip-flop circuit
4-
4-
4Mbit
No
Yes
∞
Yes
∞
25ns
25
1T with Floating Gate
Charge on Floating Gate
16Mbit
UV Erase Programmer
No
10 Years
No
100
30min
100
1T
Masked in Production
64Mbit
Mask Charges
No
∞
No
—
—
100
1T + 1T with Floating Gate
Charge on Floating Gate
3-
4Mbit
No
No
10 Years
Yes
1,000,
2.5s
200
1 SRAM Cell + 1 EEPROM Cell
SRAM + Back-Up in EEPROM
8-
9-
256K
No
No
10 years
Yes
1,000,
—
200
1T with Floating Gate
Charge on Floating Gate
64Mbit
No
No
10 Years
Yes
10,
2.5s
200
1T + 1C
Charge on Capacitor
256K
No
No
10 Years
Yes
1012
235ns
150
Source: ICE, "Memory 1997" 22610
Figure 6-2. Characteristics of MOS Memory Product Types
Lifecycle
As with any commercial product, memories have a lifecycle. A memory will pass through the dif-
ferent steps of the lifecycle, from its introduction where the IC manufacturer concentrates on cap-
ital resources and R&D efforts, to the end of its life when the product becomes obsolete.
6-4^ INTEGRATED CIRCUIT ENGINEERING CORPORATION
Year of first DRAM shipment
Minimum feature (μm)
Memory Density Bits/chip (DRAM/flash)
Logic Density (High volume: Microprocessor) Logic transistors/cm^2 (packed) Bits/cm 2 (cache SRAM)
Logic Density (Low volume: ASIC) Transistors/cm^2 (auto layout)
Number of Chip I/Os Chip to package (pads) high performance
Chip frequency (MHz) On-chip clock, cost-performance On-chip clock, high-performance Chip-to-board speed, high performance
Chip size (mm^2 ) DRAM Microprocessor ASIC
Oxide Thickness (nm)
Junction Depth (μm)
Maximum number wiring levels (logic) On-chip
Minimum mask count
Power supply voltage (V) Desktop Battery
Maximum power High performance with heatsink (W) Logic without heatsink (W/cm^2 ) Battery
64M
4M
2M
2M
256M
7M
6M
4M
1G
13M
20M
7M
4G
25M
50M
12M
16G
50M
100M
25M
64G
90M
300M
40M
Driver
D
L(μP)
L(A)
L,A
μP
L
μP
μP
μP
L
μP A
μP A L
A=ASIC L=Logic
D=DRAM
μP=Microprocessor Source: SIA/ICE, "Memory 1997" 20286C
Figure 6-4. The 15-Year SIA Roadmap
Die Size Trends
In 1975, Intel Chairman Gordon Moore predicted that engineers could shrink semiconductor
device dimensions by approximately 10 percent each year, creating a new generation of chips
every three years with four times as many transistors. Twenty one years later, Moore’s prediction
was impressively accurate. DRAM devices actually exceeded his expectations (Figure 6-5).
Figure 6-6 shows how the die area of leading-edge memory devices has increased about 13 per-
cent per year. The trend toward larger die sizes is forecast to continue. The die sizes of the 1Gbit
DRAMs described at the 1995 and 1996 ISSCC conferences ranged from 901K sq. mils to 1,451K sq.
mils (Figure 6-7). As shown, the NEC 1Gbit DRAM, if square, would be about 1.2 inches on a side.
Wafer Size
The IC industry is quickly moving to the new 300mm (12 inch) wafer standard. Figure 6-8 shows
the wafer area increase that occurs each time the industry moves to the next wafer size. Currently
the standard for high-volume advanced IC production is 200mm (8 inch). The area gained by
moving from 200mm to 300mm wafers will be 125 percent.
Advancing from one wafer size to a new, larger size takes several years of development. In fact,
development time increased substantially to transition to 200mm wafers and will be the same for
the transition to 300mm wafers (Figure 6-9). Companies such as Samsung, Texas Instruments, and
many other leading memory suppliers have indicated their willingness to build manufacturing
facilities to support 300mm wafers. The big question is which company will be the one to take on
the huge headaches and huge amount of capital needed to work out all the wrinkles associated
with the transition to 300mm wafers.
INTEGRATED CIRCUIT ENGINEERING CORPORATION 6-
Source: IEDM 40th Anniversary Edition, "Memory 1997" 19972A
Year
Moore's Curves
Limit
Logic
DRAM
1K
1M
1G
Transistors Per Chip
Figure 6-5. Growth in Chip Complexity Since 1959
Defect Density
The cost to manufacture ICs is governed by many factors. One of the most important is the
number of good dice per wafer started into the wafer fab. This number is dependent on the
number of potential dice per wafer, and the number of defective dice.
INTEGRATED CIRCUIT ENGINEERING CORPORATION 6-
Wafer Diameter Transition
100mm → 125mm
100mm → 150mm
125mm → 200mm
150mm → 200mm
200mm → 250mm
Percent Increase Source: ICE, "Memory 1997" 18603A
250mm → 300mm
200mm → 300mm
300mm → 400mm
300mm → 450mm
Figure 6-8. Wafer Area Increases (Percent)
100mm
8 years (EST)
5 years
3 years
3 years
3 years
125mm
150mm
200mm
300mm
Source: Rose Associates/ICE, "Memory 1997" 21192
Figure 6-9. Wafer Development Time Requirements (Time to Reach 100 MSI Production Rate)
Figure 6-10 shows the potential number of dice for various wafer sizes. The number of potentially
good dice per wafer is dependent on the wafer size and the die size. The number of defective dice
on a wafer are the result of random killer defects, usually expressed in defects per square cen-
timeter, and the number of defective dice caused by parametric defects. In a world class fab, the
number of dice lost because of parametric defects is very low.
As shown in Figure 6-11, random killer defects have a dramatic effect on the number of good dice
per wafer, especially as the die size increases. Figure 6-12 shows the yield effect of various defect
densities versus die size, where the yield is defined as the number of good dice divided by the
number of potential dice.
Defect density control is extremely important for memory fabs since the cell array area in a memory
IC contains extremely compact circuitry. Each generation (256Kbit, 1Mbit, 4Mbit, etc.) of memory
chip is about 50 percent larger than the previous with four times the number of bits of storage.
As feature sizes become smaller, ICs are susceptible to smaller and smaller particles causing
random killer defects. This means that if everything else remains constant, the killer defect den-
sity will increase as smaller particulates become killer defects. Yield also decreases with increas-
ing die sizes. Therefore, to maintain acceptable yields, extreme care must be taken to reduce
particulates in the ambient air, the equipment, the process gases, and the process liquids.
Fab processes themselves generate particulates that can cause defects. In modern processes, each
process step is given a defect “budget” for the number of defects per square centimeter added for
the step. As the number of process steps increases, the job of reducing the defect density becomes
more and more difficult.
Redundancy
As mentioned earlier, the effect of defect density on memory chips is a much larger problem than
with most other products due to the circuit density in the storage cell array. Nearly any particu-
late-caused defect in this area is a killer defect. To enhance memory chip yields, manufacturers
use spare rows and columns (redundant rows and columns) that can replace defective rows or
columns. During 100 percent wafer probe, defective rows and columns are “replaced” by these
spares through the use of laser blown fuses that alter the decode mechanism. When external sig-
nals try to access a defective row or column, the decode circuitry selects a spare one instead.
Figure 6-13 shows a simplified logic of redundancy programming. A normal decoder contains
half as many decoding transistors as a redundant decoder. If redundancy is not required—that is,
the chip is perfect—spare decoders will be deselected regardless of the input address.
6-8^ INTEGRATED CIRCUIT ENGINEERING CORPORATION
6-10^ INTEGRATED CIRCUIT ENGINEERING CORPORATION
8 Good Dice Out of 16 = 50%
1 Good Die Out of 4 = 25%
0 Good Die Out of 1 = 0%
Source: ICE, "Memory 1997"^ 7438B
Figure 6-11. Effect of Die Size on Yield
Defect Density
YIELD (Percent)
DIE SIZE (sq mm) 3.
DIE SIZE 32 62 93 124 155 186 217 248 279 310 341 372 403 434 465 496 527 558
(thousands of sq mils)
where A = die area in cm 2 D = defect density per cm^2
y = AD
2
Source: ICE, "Memory 1997" 14444K
1996 4M
DRAM
1996 16M
DRAM
P54CS
1996 64M
DRAM
1 – ε –AD
Figure 6-12. Murphy’s Probe Yield Model (As a Function of Defects per sq cm)
Process Complexity
Process complexity is usually measured by the number of critical mask layers, plus any special
processes that may have a detrimental effect on yield. As feature sizes have become smaller, struc-
tures under the surface of the silicon wafer have become more shallow. The structures above the
wafer surface have remained relatively thick. The thicker interconnect layers are the result of the
need to separate the conductive layers as much as possible, thus reducing the capacitive loading
of the long thin conductors (polysilicon and aluminum) running the length and width of the chip.
If the deposited dielectric films are reduced in thickness, the parasitic capacitive load will increase,
and the device will be considerably slower.
Several manufacturers have lowered the effect of parasitic capacitance through the use of materi-
als with lower dielectric constants. Polyimide is one such material. The dielectric constant of
polyimide is below 3.0, versus 3.9 for deposited silicon dioxide. The improvement in reduced par-
asitic capacitance is a linear function with respect to dielectric constant.
INTEGRATED CIRCUIT ENGINEERING CORPORATION 6-
VDD
VDD
Chip Enable, CE
A (^) o , Ao A (^) n, A n
Laser Programmable Link
VDD
VDD
A
o
A
o
A
n
A
n
CE
SPARE DECODER
Source: ICE, "Memory 1997" 17612
Figure 6-13. Row Decode for Redundancy
An extra incentive for designing 3.3V ICs is the U.S. government’s EPA Energy Star Program.
According to the EPA, computer systems account for five percent of commercial electricity con-
sumption in the United States. Energy Star mandated energy reduction in any PC the federal gov-
ernment purchased.
INTEGRATED CIRCUIT ENGINEERING CORPORATION 6-
Year Source: VLSI Technology/ICE, "Memory 1997" 19179A
5V
3V
5/3V
2.xV
Percentage of Design Starts
Figure 6-14. Transition from 5V to 3V Systems
Notebook Computer System Components
Typical 5V Power (W)
Power at 3.3V Logic (W)
Expected 3.3V Power (W)
Power (W) at 5V
Logic
Other Functions
CPU Plus Core Logic
System Memory
Display Controller Subsystem
LCD Panel Plus Backlight
Hard-Disk Drive*
Miscellaneous Circuits
DC/DC Conversion
Total System Power
*Hard-disk drive power estimates reflect a mix of active and idle time. Source: Cirrus Logic/Electronic Products/ICE, "Memory 1997" 19217
Figure 6-15. 3.3V Logic Power Savings in a Typical Notebook Computer
Process Geometries
For memory devices to become increasingly dense, feature sizes must shrink. Both gate oxides
and gate lengths need lower voltage to avoid an increase in electrical field (Figures 6-16 and 6-17).
For a similar process on a given generation, 3.3V parts have longer access times than 5V parts.
Figure 6-18 gives the supply voltage decrease versus the technology and the memory density.
Unfortunately, it is more difficult to yield high-speed devices for low voltage ICs than it is for
high voltage parts. Figure 6-19 shows a typical schmoo plot of the access time versus power
supply.
DRAMs
During 1994, there was a significant ramping-up of low-voltage DRAMs (Figure 6-20). ICE fore-
casts that in the year 2002, more than 95 percent of all DRAMs sold will be classified as low-volt-
age (3.3V or lower).
Some PC manufacturers have delayed shifting to pure 3.3V motherboard designs because price
premiums for 3.3V DRAMs would negatively impact the cost of their system. However, during
1996, all major DRAM suppliers were making the transition to 3.3V at the 16Mbit DRAM level.
6-14^ INTEGRATED CIRCUIT ENGINEERING CORPORATION
Gate Length (μm)
Gate Oxide Thickness (Å)
Published Data Trend Line
Source: Intel/ICE, "Memory 1997" 20284A
Figure 6-16. Gate Oxide Versus Gate Length
EPROMs
The development of high-density EPROMs has slowed due to the evolution of flash memories.
However, like other technologies, low-voltage parts are available. The low-voltage supply is only
used for read operations. High voltages are required for the write operations (Figure 6-21).
EEPROMs
EEPROMs must internally generate high voltage for write/erase operations. The VCC power
supply affects the internal high voltage supply (VPP). Low-voltage parts are much more complex.
There is, however, a need for low-power parts in applications such as digital cellular phones. 2.7V
to 3.6V power supply EEPROM devices are available from several vendors.
6-16^ INTEGRATED CIRCUIT ENGINEERING CORPORATION
1K 4K 16K 64K 256K 1M 4M 16M 64M 256M
1M/4M 16M 32M 64M 256M
1G
12V
5V
3.3V
1.5V
Process Technology
Year
Supply Voltage
8 μm
5 μm 3 μm
2 μm
1.3μm
0.8μm
0.5μm 0.35μm
0.25μm
0.15μm
Source: Hitachi, "Memory 1997" (^) 20872A
256 1K 4K 16K 64K 256K 1M 4M 4M 16M 64M
DRAM
SDRAM
1992/1993 1994 1995 1996 1999 FLASH
Figure 6-18. Technology Roadmap/Wafer Process
Flash Memories
Flash memories require high voltage for write and erase cycles. The first step to low voltage is to
move parts from two power supplies (12V/5V) to one power supply (5V). In this case, the high
voltage is internally generated.
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..................
V
CC
(V)
5.0V
3.3V
25ns 35ns
Source: ICE, "Memory 1997" 20821
Nanoseconds
... ... ... ... .... .... ..... ..... .................................. ................ ........................ ........................ ............ ............ ............ ............ ...... ...... ...... ...... ...... ..... ... ...... .... .
.
......... .. ..
Figure 6-19. Typical Access Time Versus Power Supply
Year
5V
Total Bits (Percent)
Source: Mitsubishi/ICE, "Memory 1997" 18623C
3.3V
Figure 6-20. Trend of Low-Voltage DRAM
Intel, also, does not support UMA. In fact, it developed another architecture called Shared
Memory Buffer Architecture (SMBA). SMBA minimizes the impact on processor performance
from sharing partitioned system memory with the graphics controller by using smart-buffering
programmable timers with a strict latency policy.
Latch-up
A major limitation to bulk CMOS technology is the inherent parasitic bipolar transistors that occur
as a natural part of the CMOS structures. The CMOS structure forms parasitic bipolar PNP and
NPN transistors that are the electrical equivalent of a silicon controlled rectifier (SCR). The para-
sitic device is electrically connected across the VDD and VSS power supply and input or output
INTEGRATED CIRCUIT ENGINEERING CORPORATION 6-
Processor
Chip Set
DRAM With Frame Buffer
GUI
Accelerator
PCI Or ISA Bus
Video Out
VESA UMA
Source: ICE, "Memory 1997" (^20871)
GUI
Accelerator
Frame Buffer
TRADITIONAL ARCHITECTURE
Processor
Chip Set
Video Out
DRAM
Figure 6-22. Traditional Memory Architecture Versus Unified Memory Architecture
Vendor
Acer Labs Cirrus Logic Opti
S Trident Micro
Via Technology VLSI Technology
Model
Aladdin lll CL-GD54UM Viper-UMA
Trio 64UV+ TGUl
Apollo VP- In Development
Target Systems
Pentium Pentium Pentium
Low-end Pentium Pentium
Pentium P54C, P6, Power PC
Clock Rate (MHz)
75-
75- 75-
75- 75-
75- 100 and up
Intel SMBA
No
No No
Yes Yes
No No
VESA-
UMA
Yes
Yes Yes
Yes Yes
Yes Yes
Remarks
Graphs Accelerator —
— Graphics Accelerator
— — Source: Electronic Business Today, "Memory 1997" 20873A
Figure 6-23. Comparing UMA Products
pads. Thus, if this parasitic device conducts, it establishes a very low resistance path to the power
supply and can cause very large amounts of current to flow through the structure. This phenom-
enon is shown in Figure 6-24. Since there are many PNPN devices on a CMOS chip, it is possible
to trigger any one device into conduction and cause the latch-up problem.
The phenomenon of latch-up is well understood by memory designers and many approaches
have been taken to eliminate it. However, the latch-up sensitivity of a CMOS circuit increases in
severity as device dimensions continue to shrink. Therefore, new latch-up reduction techniques
will be needed in the future as the process geometries become smaller.
Conditions that trigger latch-up can come from several different places in an electronic system
including over-voltage stress, voltage transients, radiation-induced photocurrents, or the input
protection circuit being over driven.
Some of the methods used to control latch-up include guard rings, epitaxy on a heavy doped sub-
strate, epitaxy/buried layer CMOS structures, Schottky clamps, physical barriers to lateral cur-
rents, trench isolation, total dielectric isolation, and well controlled design rules.
6-20^ INTEGRATED CIRCUIT ENGINEERING CORPORATION
A Anode A A
B Cathode B B
p
n
p
p
n
p
n
n
p
n
Voltage VDD
Current IH
a) transistor equivalent circuit b) I-V characteristics Source: ICE, "Memory 1997 16660B
The Four Layer Diode
(+) (–) VSS Oxide
VDD
VIN
VOUT
S (^) G D D G S
N+ P+ P+ N+ N+ P+
P– P-Well Current IRW
Substrate IRS Current
n-substrate
Figure 6-24. Bulk CMOS Inverter With pnpn Latch-Up Path
