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Memory 1997 - sec09, Notas de estudo de Automação

Complete Coverage of DRAM, SRAM, EPROM, and Flash Memory ICs,of © 1997 Integrated Circuit Engineering Corporation

Tipologia: Notas de estudo

2011

Compartilhado em 14/06/2011

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Overview
Read only memory devices are a special case of memory where, in normal system oper-
ation, the memory is read but not changed. Read only memories are non-volatile, that is,
stored information is retained when the power is removed. The main read only memory
devices are listed below:
ROM (Mask Programmable ROM —also called “MROMs”)
EPROM (UV Erasable and Electrically Programmable ROM)
OTP (One Time Programmable EPROM)
EEPROM (Electrically Erasable and Programmable ROM)
Flash Memory - These devices are covered in Section 10.
How the Device Works
The read only memory cell usu-
ally consists of a single transistor
(ROM and EPROM cells consist
of one transistor, EEPROM cells
consists of two transistors). The
gate threshold voltage of the
transistor determines whether it
is a “1” or “0”. During the read
cycle, a voltage is placed on the
gate of the cell. Depending on
the programmed threshold volt-
age, the transistor will or will not
drive a current. The sense ampli-
fier will transform this current,
or lack of current, into a “1” or
“0”. Figure 9-1 shows how a
read only memory works.
INTEGRATED CIRCUIT ENGINEERING CORPORATION
9-1
9ROM, EPROM, & EEPROM TECHNOLOGY
19956
Source: ICE, "Memory 1996"
Column
Row
Cell
Selected
Sense Amplifier
Current Detector
To Output Buffer
Figure 9-1. Read Only Memory Schematic
pf3
pf4
pf5
pf8
pf9
pfa
pfd
pfe

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Overview

Read only memory devices are a special case of memory where, in normal system oper-

ation, the memory is read but not changed. Read only memories are non-volatile, that is,

stored information is retained when the power is removed. The main read only memory

devices are listed below:

ROM (Mask Programmable ROM —also called “MROMs”)

EPROM (UV Erasable and Electrically Programmable ROM)

OTP (One Time Programmable EPROM)

EEPROM (Electrically Erasable and Programmable ROM)

Flash Memory - These devices are covered in Section 10.

How the Device Works

The read only memory cell usu-

ally consists of a single transistor

(ROM and EPROM cells consist

of one transistor, EEPROM cells

consists of two transistors). The

gate threshold voltage of the

transistor determines whether it

is a “1” or “0”. During the read

cycle, a voltage is placed on the

gate of the cell. Depending on

the programmed threshold volt-

age, the transistor will or will not

drive a current. The sense ampli-

fier will transform this current,

or lack of current, into a “1” or

“0”. Figure 9-1 shows how a

read only memory works.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 9-

Source: ICE, "Memory 1996" 19956

Column

Row

Cell Selected

Sense Amplifier Current Detector

To Output Buffer

Figure 9-1. Read Only Memory Schematic

Mask Programmable ROMs

Mask programmable ROMs (ROMs) are the least expensive type of solid state memory.

They are primarily used for storing video game software and fixed data storage for elec-

tronic equipment, such as fonts for laser printers, dictionary data in word processors, and

sound data in electronic musical instruments.

ROM programming is performed during IC fabrication. Several process alternatives can

be used to program a ROM. These are:

  • Metal contact to connect (or not to connect) a transistor to the bit line.
  • Channel implant to create either an enhancement-mode transistor or a depletion-

mode transistor.

  • Thin or thick gate oxide, which creates either a standard transistor or a high

threshold transistor, respectively.

The choice of these is a trade-off between process complexity, chip size, and manufactur-

ing cycle time. A ROM programmed at the metal contact level will have the shortest

manufacturing cycle time, as metallization is one of the last process steps. However, the

size of the cell will be larger.

Figure 9-2 shows a ROM array programmed by channel implant. The transistor cell will

have either a normal threshold (enhancement-mode device) or a very high threshold

(higher than Vcc to assure the transistor will always be off). The cell array architecture is

NOR. The different types of ROM architectures (NOR, NAND, ...) are detailed in the

flash memory section.

Figure 9-3 shows an array of storage cells (NAND architecture) that consists of single

transistors illustrated as devices 1 through 10 and 11 through 20 that is programmed with

either a normal threshold (enhancement-mode device) or a negative threshold (deple-

tion-mode device). The devices are read sequentially within the small groups. Two

groups are shown in the drawing.

In 1995, a handful of manufacturers offered 64Mbit ROM devices. Power supplies

ranged between 2.7V and 5.5V with access times in the range of 150ns. Hitachi

announced a 3.3V 16Mbit ROM with a x32bit or x16bit organization and a burst mode

(40ns access time). Random access time on the device was 120ns.

9-2^ INTEGRATED CIRCUIT ENGINEERING CORPORATION

Sharp integrated on a single chip a ROM and a Pseudo SRAM (PSRAM). Sharp called its

8Mbit device a ROM/RAM. The chip, configured 512Kbit x 16, contains 8Mbit of RAM

and 2Kbit of ROM. This device:

  • Allows RAM and ROM to be accessed at the same system speed to simplify address

management and ease software development.

  • Saves board space by combining functions that otherwise require multiple chips.

The ROM/RAM device has an access time of 80ns (170ns cycle time) and the power sup-

ply is 3V. The proposed application for DOS systems is shown in Figure 9-4.

EPROM

EPROM (UV Erasable Programmable Read Only Memory) is a special type of ROM that

is programmed in finished form (after device packaging), usually by the end user or sys-

tem manufacturer.

9-4^ INTEGRATED CIRCUIT ENGINEERING CORPORATION

Source: Sharp 19957

FFFFF

F

E

C

A

FFFFF

ROM BIOS

DOS

Expansion I/O ROM

Video RAM

Application Area

Data Area

DOS Data Interupt Vector

ROM Data Mapping

RAM

RAM

RAM

ROM

ROM

ROM

DOS System Memory

8M ROM/RAM Coexistent Memory

ROM/RAM Area

1Mbyte

Possible to arrange ROM and RAM freely together on the entire memory area.

Figure 9-4. Sharp ROM/RAM Configuration Proposal

The EPROM device is programmed by forcing an electrical charge on a small piece of

polysilicon material (called a floating storage gate) located in the memory cell. When this

charge is present on this gate, the cell is “programmed,” usually a logic “0,” and when it

is not present, it is a logic “1.” Figure 9-5 shows the cell used in a typical EPROM. The

floating gate is where the electrical charge is stored.

Prior to being programmed, an EPROM has to be erased. The EPROM is exposed to an

ultraviolet light for approximately 20 minutes through a quartz window in its ceramic

package. After erasure, new information can be programmed to the EPROM. After writ-

ing the data to the EPROM, an opaque label is placed over the quartz window to prevent

accidental erasure.

Programming is accomplished through a phenomenon called hot electron injection.

High voltages are applied to the select gate and drain connections of the cell transistor.

The select gate of the transistor is pulsed “on” causing a large drain current to flow. The

large bias voltage on the gate connection attracts electrons that penetrate the thin gate

oxide and are stored on the floating gate.

EPROM Floating Gate Transistor Characteristic Theory

The following explanation is also true for EEPROM and flash devices.

Figure 9-6 (a) and (b) shows the cross section of a conventional MOS transistor and a

floating gate transistor, respectively. The upper gate in Figure 9-6 (b) is the control gate

and the lower gate, completely isolated within the gate oxide, is the floating gate. CFG

INTEGRATED CIRCUIT ENGINEERING CORPORATION 9-

Field Oxide

P- Substrate

N+

Second-Level Polysilicon

Gate Oxide

First-Level Polysilicon (Floating)

+V G

Source: Intel 18474

Figure 9-5. Double-Poly Structure (EPROM/Flash Memory Cell)

The threshold voltage of the floating gate transistor (VTCG ) will be VTO (around 1V)

plus a term depending on the charge trapped in the floating gate. If no electrons are in

the floating gate, then VTCG = VTO (around 1V). If electrons have been trapped in the

floating gate, then VTCG = VTO - QF/CG (around 8V for a 5V part). This voltage is

process and design dependent. Figure 9-7 shows the threshold voltage shift of an

EPROM cell.

The programming (write cycle) of an EPROM takes several hundred milliseconds.

Usually a byte — eight bits — is addressed with each write cycle. The read time is com-

parable to that of fast ROMs and DRAMs (i.e., several tens of nanoseconds). In those

applications where programs are stored in EPROMs, the CPU can run at normal speeds.

Field programmability is the EPROM’s main advantage over the ROM. It allows the user

to buy mass-produced devices and program each device for a specific need. This char-

acteristic also makes the EPROM ideal for small-volume applications, as the devices are

programmed in very small quantities. Also, the systems supplier can program any last

minute upgrades to the program placed on the chip just before shipment.

EPROM cells may be configured in the NAND structure shown previously, or, more com-

monly, in the NOR configuration shown in Figure 9-8.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 9-

Programmed State (Logic "0")

Drain Current

VT0 VT

Erased State (Logic "1")

VT =

–QF

CG

Sense Threshold

Select Gate Voltage

Source: ICE, "Memory 1996" 17548A

–QF

CG

Figure 9-7. Electrical Characteristics of an EPROM

Figure 9-9 shows a Transmission Electron Microscope (TEM) cross section of an EPROM

cell. The oxide between the substrate and the floating polysilicon gate is approximately

150Å thick.

9-8^ INTEGRATED CIRCUIT ENGINEERING CORPORATION

WORD

WORD

WORD

WORD

n

BIT 1

BIT 2

19051

Select Gate

Floating Gate Source: ICE, "Memory 1996"

Figure 9-8. EPROM NOR Configuration

Figure 9-9. EPROM Cell Cross Section

Photo by ICE 19047

to 8 bits of information. A comparable digital implementation requires 3.84Mbit memory

elements to store the same amount of information. The information stored will not be 100

percent accurate but is good enough for audio applications that allows some errors.

9-10^ INTEGRATED CIRCUIT ENGINEERING CORPORATION

Source: Mitsubishi Electric

Flash Memory EPROM EEPROM

19958

Figure 9-10. Comparison of Non-Volatile Memory Cell Sizes

Metal Bit Line Polysilicon Select Gate

Deposited Oxide (^) Polysilicon Control Gate Floating Gate

N+ N+ N+

Diffused Source

Tunneling Region

Diffused Drain

Select Transistor

Memory Transistor

Source: ICE, "Memory 1996" 17551

Figure 9-11. EEPROM Cell

INTEGRATED CIRCUIT ENGINEERING CORPORATION 9-

CL 0 V

SG

CG

S

Erase

CL 0V

20V

0V

S

Program

SG

Erase

Program

Read

Unselected

VPP

V

VCC

PP

CL CG S

PP

VPP

X

PP

VPP

PP 0

SG

CL

S

Source: ICE, "Memory 1996" 17554A

CG VCC

Figure 9-12. EEPROM Cell Program/Erase

Figure 9-13. Electrical Differences Between EPROM and EEPROM

EPROM versus EEPROM

Source: ICE, "Memory 1996" 17555

Hot electron injection

1 transistor cell

Oxide ≈ 150Å

IPP current

External VPP

Fowler Nordeim tunneling

2 transistor cell

Oxide ≈ 80Å

No IPP current

Internal VPP

than DRAMs of similar feature size, but are usually designed for density and cost rather

than speed. Fast devices have access times between 20ns and 50ns and slower devices

are generally over 100ns (both in NOR structures).

Cell Size and Die Size

The cell size for the ROM is potentially the smallest of any type of memory device, as it

is a single transistor. A typical 8Mbit ROM would have a cell size of about 4.5μm^2 for a

0.7μm feature size process, and a chip area of about 76mm^2. An announced 64Mbit ROM,

manufactured with a 0.6μm feature size, has a 1.23μm^2 cell on a 200mm^2 die. The device

is wired in the NOR configuration, which improves system performance.

The ROM process is the simplest of all memory processes, usually requiring only one

layer of polysilicon and one layer of metal. There are no special film deposition or etch

requirements, so yields are the highest of all memory chips of the same density.

The cell size of the EPROM is also relatively small. The EPROM requires one additional

polysilicon layer, and will usually have slightly lower yields due to the requirement for

nearly perfect (and thin) gate oxides.

These factors, plus the fact that an EPROM is encased in a ceramic package with a quartz

window, make the EPROM average selling price three to five times the price of the mask

ROM.

There are two distinct EEPROM families: serial and parallel access. The serial access

represents 90 percent of the overall EEPROM market.

Serial access EEPROMs feature low pin count. Typically they are packaged in an 8-pin

package:

  • 2 pins for power voltage,
  • 1 pin for Read/Write control,
  • 1 pin for the clock,
  • 1 pin for Input/Output,
  • 3 pins for Chip Enable.

Serial EEPROMs are readily available in low densities (typically from 256 bit to 256Kbit).

Parallel EEPROMs typically start at the 256Kbit level and increase to bigger densities.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 9-

The EEPROM requires much more silicon area per bit because of the access transistor

required for each cell. However, the EEPROM structure will continue to be used in those

ROM applications where erasure on a bit level is needed.

Figure 9-15 shows the physical geometries of EPROMs and EEPROMs analyzed by the

ICE laboratory in 1995.

9-14^ INTEGRATED CIRCUIT ENGINEERING CORPORATION

Technology

Die Size

Min Gate - (N)

Cell Pitch

Cell Area

EEPROM

5.7 x 8.9mm (51mm 2 )

1.3μm

2.6 x 8.1μm

21 μm 2

EEPROM

6.1 x 8.2mm (50mm 2 )

0.6μm

4.25 x 5.3μm

22.5μm 2

EPROM

3.4 x 4.3mm (14.6mm 2 )

0.6μm

2.1 x 2.1μm

4.4μm 2

EPROM

4 x 4.5mm (18mm 2 )

0.7μm

2.5 x 2.7μm

6.8μm 2

XICOR

XC28C

1Mbit 9443

HITACHI

HN58C1001P-

1Mbit 1994 - 1995

ATMEL

AT27C010-

1Mbit 9428

ISSI

IS27HC

1Mbit 1994 - 1995

Source: ICE, "Memory 1996" 20847

Figure 9-15. Physical Geometries of EPROMs and EEPROMs