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OVERVIEW
DRAM (Dynamic Random Access Memory) is the main memory used for all desktop and larger
computers. Each elementary DRAM cell is made up of a single MOS transistor and a storage
capacitor (Figure 7-1). Each storage cell contains one bit of information. This charge, however,
leaks off the capacitor due to the sub-threshold current of the cell transistor. Therefore, the charge
must be refreshed several times each second.
HOW THE DEVICE WORKS
The memory cell is written to by placing a “1” or “0” charge into the capacitor cell. This is done
during a write cycle by opening the cell transistor (gate to power supply or VCC) and presenting
either VCC or 0V (ground) at the capacitor. The word line (gate of the transistor) is then held at
ground to isolate the capacitor charge. This capacitor will be accessed for either a new write, a
read, or a refresh.
Figure 7-2 shows a simplified DRAM diagram. The gates of the memory cells are tied to the
rows. The read (or write) of a DRAM is done in two main steps as illustrated in Figure 7-3. The
row (X) and column (Y) addresses are presented on the same pads and multiplexed. The first
step consists of validating the row addresses and the second step consists of validating the
column addresses.
INTEGRATED CIRCUIT ENGINEERING CORPORATION 7-
Word Line
Bit Line
Transistor
Capacitor
Plate
Source: ICE, "Memory 1997" 19941
Figure 7-1. DRAM Cell
7-2^ INTEGRATED CIRCUIT ENGINEERING CORPORATION
Data
Data
Sense Amplifier
Data
Data
Sense Amplifier
Data
Data
Sense Amplifier
Data
Data Sense Amplifier
Output Buffer
Dout
Y Decode
CAS
Y
X
RAS
Address Pads Row Decode
Source: ICE, "Memory 1997" 22430
Din Input Buffer
Figure 7-2. Simplified DRAM Diagram
Figure 7-3. DRAM Access Timing
Step I
Row Access
Step II
Column Access
Address Row Column
RAS
CAS
Source: ICE, "Memory 1997" 22431
For standard DRAMs there are three ways to perform refresh cycles. They are RAS-only refresh,
CAS-before-RAS refresh, and hidden refresh. To perform a RAS-only refresh, a row address is put
on the address lines and then RAS goes low. To perform a CAS-before-RAS refresh, CAS first goes
low and then a refresh cycle is performed each time RAS goes low. To perform a hidden refresh
the user does a read or write cycle and then brings RAS high and then low.
MEMORY CELL
A great deal of design effort has been made to shrink the cell area, particularly, the size of the
DRAM capacitor. As memory density increases, the cell size must decrease. Designers have man-
aged to shrink overall cell size. However, due to factors such as noise sensitivity and speed, it has
been a challenge to reduce the capacitance. The capacitance must stay in the range of 30fF.
The charge (Q) stored in a capacitor is equal to capacitance times voltage (Q = C x V). Over the
years, DRAM operating voltage has decreased (i.e., 12V to 5V to 3.3V). As voltage decreases, the
stored charge will also decrease. Design improvements allow for the decrease in the cell charge
as long as the capacitance remains in the range of 30fF.
Two main developments are used to reduce capacitor area without reducing its value. These are
the use of new capacitor shapes to fit into a minimum chip surface area and increasing the
dielectric constant.
Memory Cell Shape
The 1Mbit DRAM generation was the first to abandon the classical planar capacitor and replace it
with a trench or a stacked capacitor. Figure 7-5 shows the feature sizes of some of the DRAM
devices that ICE analyzed in its laboratory these two last years. Trench capacitors are not widely
used in spite of continual research and development on that type of design. As shown, the major
64Mbit DRAMs available on the market are today made of stacked capacitors.
7-4^ INTEGRATED CIRCUIT ENGINEERING CORPORATION
Distributed Refresh
Burst Refresh
Each Pulse Represents a Refresh Cycle
Time Required Time To Complete Refresh Of All Rows
Source: Micron, "Memory 1997" 20843
Figure 7-4. Burst and Distributed Refresh
Cross sections of 64Mbit DRAMs analyzed by ICE’s laboratory illustrate three major choices for
manufacturing DRAM memory cells. Hitachi uses a stacked, multi-layer capacitor for its 64Mbit
DRAM (Figure 7-6). The trench capacitor (Figure 7-7) is used by IBM/Siemens, and the simple
stack capacitor (Figure 7-8, and 7-9) is preferred by Samsung and NEC.
Figure 7-10 shows how size cell improvements will be necessary for the next DRAM generations.
Figure 7-11 illustrates the stacked capacitor structure evolution. The decrease of cell size without
decreasing capacitor value results in increasing complexity of memory cell technology. Most lead-
ing DRAM manufacturers are working on 1Gbit cells. Their goal is to decrease the size of the cell
without compromising the value of the capacitor.
Two types of 1Gbit cell developments are shown in the next figures. Toshiba tried to improve the
trench capacitor concept by creating a bottle-shape trench design (Figure 7-12). Hitachi tried to
improve the stack concept with a vertical and circular capacitor (Figure 7-13). NEC received a
patent from the U.S. Patent Office for its proprietary HSG (hemispherical-grain) silicon technology.
INTEGRATED CIRCUIT ENGINEERING CORPORATION 7-
Source: ICE, "Memory 1997" 22432
Fujitsu Mosel-Vitelic
NEC IBM/Siemens Samsung
Mitsubishi Hitachi
16M
4M
64M
64M
64M
16M
64M
Stacked Stacked
Stacked Trench Crown
Stacked Stacked
Density Date Code Cell Area μm^
Die Area mm^
Name Gate Length Cell Type
Figure 7-5. Physical Dimensions of DRAMs
Figure 7-6. Hitachi 64Mbit DRAM Cross Section
Photo by ICE, “Memory 1997” 19814
CAPACITOR DIELECTRICS
The inability to scale the capacitor value has led to the consideration of new dielectric materials for
the capacitor. It is likely that materials with higher dielectrics will see more use. Many of the mate-
rials have proven track records through their use as dielectrics in discrete capacitors. Therefore, the
main challenge is the introduction of these materials into the IC process. Figure 7-14 shows some
of the materials under consideration. Tantalum Pentoxide (Ta 2 O 5 ) has been viewed in several of
the 64Mbit DRAMs analyzed by the ICE laboratory. Ta 2 O 5 seems that it could serve as a good
dielectric since it can easily be integrated into conventional stack capacitor structure. However, it
requires higher dielectric thickness, resulting in only a marginal improvement in capacitance.
PERFORMANCE
Compared with other memory ICs, DRAMs suffer from a speed problem. The on-chip circuitry
required to read the data from each cell is inherently slow. As such, DRAM speeds have not kept
pace with the increased clock speed of CPUs.
INTEGRATED CIRCUIT ENGINEERING CORPORATION 7-
256K 1M 4M 16M 64M 256M 1G 4G
10 -
1
10 1
102
103 10
DRAM Generation (bits)
Chip Area (mm
2 ), Cell Area (
μ
m
2 )
Minimum Feature Size (
μm
2 )
Source: Hitachi/ICE, "Memory 1997" 20775A
Cell Area
Chip Area
Minimum Feature Size
Figure 7-10. DRAM Technology Trend
7-8^ INTEGRATED CIRCUIT ENGINEERING CORPORATION
Planar
Cup
Simple Stack
Simple Crown
HSG Crown
Multilayer Fin
Multilayer Crown
Source: IBM/Semiconductor International/ICE, "Memory 1997" 22435
Figure 7-11. Stack Capacitor Structure Evolution
Figure 7-12. Capacitor Manufacturing Process
Si RIE In-situ Doped Poly-Si Deposition
Annealing
Impurity Doping Into the Plate Electrode
Chemical Dry Etching
Source: Toshiba/ICE, "Memory 1997" 20767
Fast Page Mode DRAMs
To access DRAM data, a row address is applied, followed by a column address. The addresses of
a DRAM are multiplexed on the same package pins. When requested data is stored in the same
row as previously requested data, merely changing the column address allows access to this new
data. Therefore, with fast page mode, the data of the same row can be accessed by changing only
the column address.
As an example, consider a 1Mbit DRAM that has an array organization of 1,024 x 1,024 bits. 1,
bits of data belong to the same row. This data will be accessible through fast page mode (a row is
considered a page). This mode is available on all the standard DRAMs. As described previously,
this access time is as fast as the data available in the sense amplifier.
7-10^ INTEGRATED CIRCUIT ENGINEERING CORPORATION
Source: ICE, "Memory 1997" 22450
Standard
Cache
Synchronous
Cache Synchronous
Video
Pseudo Static
Other Configurations
Other Technology
DRAM
FPM (Fast Page Mode) EDO (Extended Data Out) BEDO (Burst EDO) ARAM (Audio RAM)
EDRAM (Enhanced DRAM) CDRAM (Cache DRAM)
SDRAM (Synchronous DRAM)
SDRAM II or DDR DRAM (Double Data Rate DRAM)
SGRAM (Synchronous Graphic DRAM)
ESDRAM (Enhanced SDRAM)
VRAM (Video RAM) WRAM (Window RAM)
PSDRAM (Pseudo Static RAM) Fusion
RDRAM (Rambus) SLDRAM (SyncLink) 3D
nDRAM (Next Generation) MDRAM (Multi Bank)
FRAM (Ferroelectric DRAM)
Figure 7-15. Current DRAM Varieties
Static column mode is similar to page mode except that only the column address needs to be
changed to obtain the new data, and no CAS pulse is needed. Nibble mode groups memory cells
in “four bits per nibble” so that whenever one bit is selected, four serial bits appear. This mode is
no longer widely used.
Extended Data Out (EDO) DRAMs
Extended data out DRAMs (EDO DRAMs), also called hyper-page-mode DRAMs, represent a
small design change in the output buffer relative to a standard fast page mode DRAM. The old
data is latched at the output while new data is addressed. EDO shortens the effective page mode
cycle time as the valid data output time is extended.
For the same technology, a product in standard mode may have a cycle time of 110ns (access time
of 60ns). This cycle time will be reduced to 40ns in fast page mode and to 25ns in EDO mode.
Burst EDO DRAMs
Several vendors offer burst versions of the EDO DRAM. The “burst” refers to the fact that all read
and write cycles occur in bursts of four, automatically sequenced by the memory chip. To accom-
plish that, a special pipeline stage and a two-bit counter are added.
The Burst EDO DRAM read access time differs from EDO DRAM in two ways. First, as the output
latch is replaced by a special pipeline stage (register), the latency will be higher but the bandwidth
will be better. Second, as the Burst EDO DRAM includes an internal address counter, only the ini-
tial address in a burst of four needs to be provided.
Manufacturers may use the same mask set for their fast page mode EDO and burst EDO DRAMs.
A wire bond option determines which product is in the final package. Figure 7-16 shows timing
differences between the various standard DRAMs. Figure 7-17 shows speed differences.
Audio DRAMs
Due to process defects during wafer probe, some DRAMs wind up with a few failed storage cells
that cannot be effectively repaired (or replaced) by the redundancy mechanism. These cannot
be sold as good devices to PC OEMs. However, a few defective bits do not affect an audio appli-
cation where there is a tolerance for error. For this reason manufacturers may sell parts with few
bad cells for use in audio applications. These devices are called Audio DRAM (ARAM). The
client can buy ARAMs cheaper than a standard DRAM.
INTEGRATED CIRCUIT ENGINEERING CORPORATION 7-
Enhanced DRAMs
Enhanced DRAMs (EDRAMs) were developed by Ramtron Corporation. The EDRAM is also sold
by IBM (3.3V and 5V parts), as IBM and Ramtron have a second source agreement for this prod-
uct. The EDRAM architecture is similar to a standard 4Mbit page mode or static column DRAM
with the addition of an integrated L2 SRAM cache and internal control. Technically, the EDRAM
is a cache DRAM (CDRAM). Rather than integrate a separate SRAM cache, the EDRAM takes
advantage of the internal architecture of a standard fast page mode DRAM, which has sense
amplifiers that act like a 2Kbit SRAM cache when reading and accessing data.
Memory read cycles always occur from the cache. When the comparator detects a hit, only the
SRAM is addressed where data is available in 15ns. When a miss is detected, the entire cache is
updated and data is available at the output within a single 35ns access. Figure 7-19 shows the chip
organization of an EDRAM.
INTEGRATED CIRCUIT ENGINEERING CORPORATION 7-
SRAM
Address
Address Latch
Address Latch
4K x 4 Fast SRAM Cache
Clock
Cache Hit
CS, Write Enable
Control
Refresh
Multiplexed DRAM Address
DRAM
Control
1M x 4 DRAM Array
64-Bit Buffer 64-Bit Buffer Data
Source: EBN/ICE, "Memory 1997" 20756
Figure 7-18. Cache DRAM
Column Address Latch
Last Row Read Address Latch
Row Address Latch
Flow Address and Refresh Counter Refresh Address
512 x 4 Page Cache (SRAM)
Column Decoder
Sense Amps and Write Select
DRAM Array (2,048 x 512 x 4)
Read Data
Write Data
Ground
Set
Write Enable
Data
I/O
Control and Data Latches
Column Access Signal
Address Lines
Refresh Control Pin Read/Write Control Row Access Signal Source: EBN/ICE, "Memory 1997" 20757
Figure 7-19. Enhanced DRAM (EDRAM)
Synchronous DRAMs
Synchronous DRAMs represent the next step in the evolution of the industry standard DRAM
architecture. Synchronous DRAMs (SDRAMs) have their read and write cycles synchronized
with the processor clock. The SDRAM is designed with two separate banks. These two indepen-
dent banks allow each bank to have different rows active at the same time. This allows concur-
rent access/refresh and recharge operations. Figure 7-20 presents a block diagram organization
of an SDRAM.
The SDRAM is programmed using a mode register. The programmable features include burst
length (1, 2, 4, 8, full page), wrap sequence (sequential/interleave), and CAS latency (1, 2, 3).
Figure 7-21 shows an SDRAM timing sequence. This timing illustrates the different possibilities
of CAS latency and of burst length.
7-14^ INTEGRATED CIRCUIT ENGINEERING CORPORATION
Figure 7-20. 4Mbit SDRAM Block Diagram
Input Latch /Buffer
Output Latch
Output Latch
Output Buffer
Data Bus
Control Logic and Timing Generator
Address Bus
Burst Counter Column Address Latch Row Address Latch
Refresh Counter
MUX
Row Decorder Row Decorder
Memory Array Bank 0 Memory Array Bank 1 ColumnDecoder Sense Amps
ColumnDecoder Sense Amps
Columns
Columns
CAS
Latency Control
512 Rows 512 Rows
Mode Register
A9-A
A
A9 A7-A0 A9-A
A9-A
DQMUDQMLWE#CAS#RAS#CS#CKECLK
Source: Hitachi/ICE, "Memory 1997" 22437
7-16^ INTEGRATED CIRCUIT ENGINEERING CORPORATION
F.P. = Full Page R = Reserved (inhibit)
A9 A8 A7 A6 A5 A4 A3 A2 A1 A OPCODE 0 LMODE BT BL
A 0 0 0 0 1
A 0 0 1 1 X
A 0 1 0 1 X
CAS Latency R 1 2 3 R
A 0 1
Burst Type Sequential Interleave
A2 A1 A
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 R 2 4 8 R R R
F.P.
BT=0 BT= R 2 4 8 R R R R
Burst Length
A 0 0 1 1
A 0 1 0 1
Burst Read and Burst Write R Burst Read and Single Write R
Write Mode
Source: Hitachi/ICE, "Memory 1997" 22438
Figure 7-22. Register Content of a 4Mbit SDRAM
Figure 7-23. SDRAM Functionality
CLK: External Clock Input and Synchronous DRAM Operations Synchronize with this Signal
Command: Controls Synchronous DRAM Operation Command is a Combination of CS, RAS, CAS, and WE Signals.
Active Read
Row Column
BS BS
Bank Select: A Memory Contains 2 Banks (Areas) that can be Controlled Independently. BANK SELECT is used to Select a Bank.
Command (CS,RAS,CAS,WE)
CLK
Address (A0 to A8)
Bank Select (A9)
Dout Out 0 Out 1 Out 2 Out 3
CAS Latency = 3 Burst Length = 4
CAS Latency: Clock Numbers from Read Command Set to Data Output
Burst Length: Possible Consecutive Input/Output Data Length
Active Command Set Cycle
Read Command Set Cycle
Source: Hitachi/ICE, "Memory 1997" 22440
Synchronous Graphics RAMs
Synchronous Graphics RAMs (SGRAMs) target video applications. SGRAMs differ from
Synchronous DRAMs (SDRAMs) in that they provide features traditionally associated with video
DRAMs such as 32-bit-wide bus and graphics-specific features such as block write mode and a
masked write mode. Figure 7-24 shows the chip organization of an SGRAM.
Enhanced Synchronous DRAMs
Enhanced Memory Systems Inc., a subsidiary of Ramtron, developed its Enhanced Synchronous
DRAMs (ESDRAM). This memory combines the features of SDRAM plus cache SRAM on the same
chip. 16Mbit ESDRAM combines two banks of 8Mbit SDRAM plus two banks of 4Kbit SRAM.
Video DRAMs
Video DRAMs (VRAMs) are also called Dual-Port DRAMs. VRAMs are almost exclusively used
for video applications. Since the standard DRAM is inherently parallel and video data is inher-
ently serial, graphics systems have always needed parallel to serial shift registers. A VRAM has
separate parallel and serial interfaces. For example, a 4Mbit DRAM may be organized as:
DRAM: 262,144 Words X 16 bits
SAM (Serial Access Memory): 256 Words X 16 bits
INTEGRATED CIRCUIT ENGINEERING CORPORATION 7-
Multiplexed Address (^) Address Register
Refresh Counter (^) Row Address
Column Address
DRAM Memory Array 2M x 16 (one or two banks)
Data I/O Buffer
Timing and Control Logic
Clock (^) Clock Enable
Row Access Signal
Column Access Signal
Write Enable
Data
Source: EBN/ICE, "Memory 1997" (^20763)
Color Register
Mask Register
32 Bits
Figure 7-24. Synchronous Graphic DRAM
Although they have been available for more than 15 years, the PSRAMs market has never grown
strongly. Moreover, it seems that the PSRAM market may be shriveling as Hitachi and Toshiba,
the two major suppliers withdraw support. Figure 7-27 provides a comparison of PSRAMs and
low-power SRAMs.
Fusion Memories
Integrated Device Technology (IDT) developed a pseudo static DRAM and SRAM and labeled it
fusion memory. IDT claims that fusion memory is the first architecture to fuse together SRAM
performance at DRAM density and cost.
INTEGRATED CIRCUIT ENGINEERING CORPORATION 7-
512 Row Add Decoder
512 Column Decoder x 32
512 Sense Amps x 32
DRAM
32 Planes 512 x 512 Latch 0 Latch 1 Latch 2 Latch 3 SRAM Array 8 x 8 x 32 Write and Byte Mask Control
Color Reg 0 Color Reg 1
I/O Sense Amp x 32
256-Bit Internal Data Bus
8:1 Mux
32 DQ Lines
Serial Out
2:1 Mux 16
32 Data Buffers
Source: EBN/ICE, "Memory 1997" (^20755)
Figure 7-26. Window DRAM
4M
SRAM
4M
PSRAM
55ns
90mA 15 μa @ 2V 4x
80ns
75mA 15 μa @ 3V 1.2x
Source: ICE, "Memory 1997" 18742
Access Time
Operating Current Data Retention Power Relative per Bit Cost (DRAM = 1)
Figure 7-27. Static and Pseudo Static RAM Comparison
Rambus DRAMs
Rambus technology is based on very high speed, chip-to-chip interface that is incorporated on a
new DRAM architecture and on processors or controllers. The Rambus architecture achieves a
performance level more than ten times greater than conventional DRAMs. Rambus Inc. does not
manufacture products but licenses its design of Rambus DRAMs (RDRAMs) and controllers. To
date, Rambus has licensed over one dozen of the world’s largest semiconductor companies to
jointly develop and bring to market a wide range of memory and logic products. Further, it won
the support of Intel for the next-generation of DRAM architecture in PC systems.
Unlike other approaches that have focused on increasing the speed of individual DRAMs,
Rambus provides a complete system-level solution by integrating fast components with an inno-
vative high-speed interface technology. Figure 7-28 shows the Rambus technology elements. This
architecture is comprised of three main elements that include the Rambus Channel, the Rambus
Interface (controller), and the RDRAMs.
The Rambus Channel
Figures 7-29 through 7-31 show the configuration and the main characteristics of the Rambus
Channel. The Rambus Channel is the core of Rambus’ architecture. The goal of this channel is to
transmit information at a very high rate. For that to occur, the conventional TTL level signals are
replaced by small swing (600mV) signals plus an additional reference signal (Vref) set to be the
mid-point of the swing. These low-speed signals reduce bus power consumption, noise, and
increase the speed transfer.
7-20^ INTEGRATED CIRCUIT ENGINEERING CORPORATION
CPU
Controller (ASIC)
RDRAM 1 RDRAM 2 RDRAM 3 RDRAMn
Rambus Channel
Source: ICE, "Memory 1997" 22443
Figure 7-28. Typical Rambus Configuration
